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參數(shù)資料
| 型號： | TSB12C01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 7/59頁 |
| 文件大小： | 275K |
| 代理商： | TSB12C01APZ |
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1–1
1 Overview
1.1
Description
The TSB12C01A is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed
serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12C01A
transmits and receives correctly formatted 1394 packets and generates and inspects the 32-bit cyclic
redundancy check (CRC). The TSB12C01A is capable of being a cycle master and supports reception of
isochronous data on two channels. It interfaces directly to the TSB11C01, TSB11LV01, and TSB21LV03
physical-layer chips and can support bus speeds of 100, 200, and 400 Mb/s. The TSB12C01A has a generic
32-bit host bus interface, which makes connection to most 32-bit host buses very simple. The TSB12C01A
has software-adjustable FIFOs for optimal FIFO size and performance characterization and allows for
variable-size asynchronous-transmit FIFO (ATF), isochronous-transmit FIFO (ITF), and general-receive
FIFO (GRF).
This document is not intended to serve as a tutorial on 1394; users should refer to the IEEE 1394-1995 serial
bus for detailed information regarding the 1394 high-speed serial bus.
1.2
The following are features of the TSB12C01A.
Features
1.2.1
Link
Complies With IEEE-1394-1995 Standard
Transmits and Receives Correctly Formatted 1394 Packets
Supports Isochronous Data Transfer
Performs Function of Cycle Master
Generates and Checks 32-Bit CRC
Detects Lost Cycle-Start Messages
Contains Asynchronous, Isochronous, and General-Receive FIFOs
1.2.2
Physical-Link Interface
Interfaces Directly to the TSB11C01, TSB11LV01, TSB14C01, and TSB21LV03 Phy Chips
Supports Speeds of 100, 200, and 400 Mb/s
Implements the Physical-Link Interface Described in Annex J of the IEEE 1394-1995 Standard
Supports TI Bus Holder Isolation External Implementation
1.2.3
Host Bus Interface
Provides Chip Control With Directly Addressable Registers
Is Interrupt Driven to Minimize Host Polling
Has a Generic 32-Bit Host Bus Interface
1.2.4
General
Requires a Single 5-V
±
5% Power Supply
Manufactured with Low-Power CMOS Technology
Packaged in a 100-Pin Thin Quad Flat Package (TQFP) (PZ Package) for 0
°
C to 70
°
C and –40
°
C
to 85
°
C Operation
Packaged in a 100-Pin Ceramic Quad Flat Package (WN Package) for –55
°
C to 125
°
C Operation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TSB12C01AWN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:High-Speed Serial-Bus Link-Layer Controller |
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