參數(shù)資料
型號： TSB12C01APZ
廠商： Texas Instruments, Inc.
英文描述： High-Speed Serial-Bus Link-Layer Controller
中文描述： 高速串行總線鏈路層控制器
文件頁數(shù)： 43/59頁
文件大小： 275K
代理商： TSB12C01APZ
5–3
5.4
Host-Interface Timing Requirements, T
A
= 25
°
C (see Note 5)
PARAMETER
MIN
MAX
UNIT
tc1
tw1(H)
tw1(L)
tsu1
th1
tsu2
th2
tsu3
th3
tsu4
th4
NOTE 5: These parameters are not production tested.
Cycle time, BCLK (see Figure 6–1)
30
111
ns
Pulse duration, BCLK high (see Figure 6–1)
10
ns
Pulse duration, BCLK low (see Figure 6–1)
Setup time, DATA0 – DATA31 valid before BCLK
↑
(see Figure 6–2)
Hold time, DATA0 – DATA31 invalid after BCLK
↑
(see Figure 6–2)
Setup time, ADDR0 – ADDR7 valid before BCLK
↑
(see Figures 6–2 and 6–3)
Hold time, ADDR0 – ADDR7 invalid after BCLK
↑
(see Figures 6–2 and 6–3)
Setup time, CS
↓
before BCLK
↑
(see Figures 6–2 and 6–3)
Hold time, CS
↑
after BCLK
↑
(see Figures 6–2 and 6–3)
Setup time, WR valid before BCLK
↑
(see Figures 6–2 and 6–3)
Hold time, WR invalid after BCLK
↑
(see Figures 6–2 and 6–3)
10
ns
4
ns
2
ns
12
ns
2
ns
12
ns
2
ns
12
ns
2
ns
5.5
Host-Interface Switching Characteristics Over Operating Free-Air
Temperature Range of 0
°
C to 70
°
C, C
L
= 45 pF (unless otherwise noted)
PARAMETER
Delay time, BCLK
↑
to CA
↓
(see Figure 6–2)
Delay time, BCLK
↑
to CA
↑
(see Figure 6–2)
Delay time, BCLK
↑
to DATA0 – DATA31 valid (see Figure 6–3 and Note 5)
Delay time, BCLK
↑
to DATA0 – DATA31 invalid (see Figure 6–3 and Note 5)
NOTE 5: These parameters are not production tested.
MIN
MAX
UNIT
td1
td2
td3
td4
4
16
ns
4
16
ns
4
24
ns
4
24
ns
5.6
Phy-Interface Timing Requirements Over Operating Free-Air
Temperature Range of 0
°
C to 70
°
C (see Note 5)
PARAMETER
MIN
MAX
UNIT
tc2
tw2(H)
tw2(L)
tsu5
th5
tsu6
th6
NOTE 5: These parameters are not production tested.
Cycle time, SCLK (see Figure 6–4)
20.24
20.45
ns
Pulse duration, SCLK high (see Figure 6–4)
9
ns
Pulse duration, SCLK low (see Figure 6–4)
Setup time, D0 – D7 valid before SCLK
↑
(see Figure 6–6)
Hold time, D0 – D7 invalid after SCLK
↑
(see Figure 6–6)
Setup time, CTL0 – CTL1 valid before SCLK
↑
(see Figure 6–6)
Hold time, CTL0 – CTL1 invalid after SCLK
↑
(see Figure 6–6)
9
ns
6
ns
1
ns
6
ns
1
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12C01AWN 制造商:TI 制造商全稱:Texas Instruments 功能描述:High-Speed Serial-Bus Link-Layer Controller
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TSB12LV01APZ 制造商:TI 制造商全稱:Texas Instruments 功能描述:High-Speed Serial-Bus Link-Layer Controller
TSB12LV01B 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER
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