
7–3
7.5.1.2
TSB12C01A Read-Register Request
Table 7–5. Read-Register Request Functions (Length of Stream: 9 Bits)
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Start bit indicates the beginning of the transfer (always set).
1–3
Request Type
Request type indicates the type of request function (see Table 7–7 for the encoding of this
field).
4–7
Address
These bits contain the address of the phy register to be read.
8
Stop Bit
Stop bit indicates the end of the transfer (always cleared).
7.5.1.3
TSB12C01A Write-Register Request
Table 7–6. Write-Register Request (Length of Stream: 17 Bits)
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Start bit indicates the beginning of the transfer (always set).
1–3
Request Type
Request type indicates the type of request (see Table 7–7 for the encoding of this field).
4–7
Address
These bits contain the address of the phy register to be written to.
8–15
Data
These bits contain the data that is to be written to the specified register address.
16
Stop Bit
Stop bit indicates the end of the transfer (always cleared).
7.5.1.4
Request-Type Field for TSB12C01A Request
Table 7–7. TSB12C01A Request Functions
LREQ1 –
LREQ3
NAME
DESCRIPTION
000
TakeBus
Immediate request. Upon detection of an idle, take control of the bus immediately (no
arbitration) for asynchronous packet ACK response.
001
IsoReq
Isochronous request. IsoReq arbitrates for control of the bus after an isochronous gap.
010
PriReq
Priority request. PriReq arbitrates for control of the bus after a fair gap and ignores fair
protocol.
011
FairReq
Fair request. FairReq arbitrates for control of the bus after a fair gap and uses fair protocol.
100
RdReg
Read request. RdReg returns the specified register contents through a status transfer.
101
WrReg
Write request. WrReg writes to the specified register.
110, 111
Reserved
Reserved
7.5.1.5
Request-Speed Field for TSB12C01A Request
Table 7–8. TSB12C01A Request-Speed Functions
LREQ4, LREQ5
DATA RATE
00
100 Mb/s
01
200 Mb/s
10
400 Mb/s
11
Reserved