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| 型號： | TSB12C01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 24/59頁 |
| 文件大?。?/td> | 275K |
| 代理商： | TSB12C01APZ |
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3–8
3.2.6
The isochronous receive-port number register controls which isochronous channels are received by this
node. This register is at address 18h. The register is read/write, and its initial value is 0000_0000h.
Isochronous Receive-Port Number Register
Table 3–6. Isochronous Receive-Port Number Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0–7
IRPort1
Isochronous receive
TAG bits and port 1
channel number
IRPort1 contains the channel number of the isochronous packets the
receiver accepts when IRP1En is set (bits 0 and 1 are reserved as
TAG bits). See Table 4–5 and Table 4–6 for more information.
8–15
IRPort2
Isochronous receive
TAG bits and port 2
channel number
IRPort2 contains the channel number of the isochronous packets the
receiver accepts when IRP2En is set (bits 8 and 9 are reserved as
TAG bits). See Table 4–5 and Table 4–6 for more information.
16–31
Reserved
Reserved
Reserved
3.2.7
The diagnostic control and status register allows for the monitoring and control of the diagnostic features
of the TSB12C01A. The register is at address 20h. The regRW and enable snoop bits are read/write. When
regRW is cleared, all other bits are read only. When regRW is set, all bits are read/write. Its initial value is
0000_0000h. For a RAM test read/write, enable RAM test mode and set Adr_clr to clear the RAM internal
address counter. Do the host bus read/write to location 80h; this accesses RAM starting at location 00h.
With each read/write the RAM internal address counter increments by one.
Diagnostic Control and Status Register
Table 3–7. Diagnostic Control and Status-Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0
ENSp
Enable Snoop
When ENSp is set, the receiver accepts all packets on the bus
regardless of address or format. The receiver uses the snoop data
format defined in Section 4.4.
1
BsyFl
Busy flag
When BsyFl is set, the receiver sends an ack_busyB the next time the
receiver must busy a packet. When cleared, the receiver sends an
ack_busyA the next time the receiver must busy a packet.
2
ArbGp
Arbitration reset
gap
When ArbGp is set, the serial bus has been idle for an arbitration reset
gap.
3
FrGp
Fair gap
When FrGp is set, the serial bus has been idle for a fair-gap time
(Sub-Action Gap).
4
regR/W
Register read/write
access
When regR/W is set, most registers are fully read/write.
5
Adr_clr
Address clear
When Adr_clr is set, the internal RAM address counter and the
Control_bit_err flag are cleared.
6
Control_bit1
Control bit for RAM
test write
During RAM test mode, Control_bit1 is written into the control bit of
RAM (bit 33) for RAM write transaction.
7
Control_bit_err
Control bit error
flag
When Control_bit_err is set, the control bit of the RAM does not
match Control_bit1 during RAM test mode.
8
RAMTest
RAM test mode
When RAMTest and regRW are set, RAM test mode is enabled.
9–31
Reserved
Reserved
Reserved
3.2.8
The phy-chip access register allows access to the registers in the attached phy chip. The most significant
16 bits send read and write requests to the phy-chip registers. The least significant 16 bits are for the phy
chip to respond to a read request sent by the TSB12C01A. The phy-chip access register also allows the
phy interface to send important information back to the TSB12C01A. When the phy interface sends new
Phy-Chip Access Register
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