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參數(shù)資料
| 型號： | TSB12C01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 22/59頁 |
| 文件大?。?/td> | 275K |
| 代理商： | TSB12C01APZ |
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3–6
Set
Clear
Clk
PhInt Bit
Interrupt Bit (INT)
Other
Interrupts
Interrupt Bit
IntMask Bit
PhInt Bit
PhIntMask Bit
INT
DATA (01)
CS
WR
PhInt Source
SCLK
Q
Figure 3–2. Interrupt Logic Diagram Example
Table 3–4. Interrupt- and Mask-Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0
Int
Interrupt
Int contains the value of all interrupt and interrupt mask bits ORed
together.
1
PhInt
Phy chip interrupt
When PhInt is set, the phy chip has signaled an interrupt through the
Phy interface.
2
PhyRRx
Phy register
information received
When PhyRRx is set, a register value has been transferred to the phy
chip access register (offset 24h) from the phy interface.
3
PhRst
Phy reset started
When PhRst is set, a phy-layer reconfiguration has started (1394 bus
reset).
4
Reserved
Reserved
Reserved
5
TxRdy
Transmitter ready
When TxRdy is set, the transmitter is idle and ready.
6
RxDta
Receiver has data
In normal mode and when set, RxDta indicates that the receiver has
accepted a quadlet of data into the GRF interface. This bit is set each
time a quadlet of data is accepted. However, during the self-ID portion
of a bus reset, this bit is set after each complete self-ID packet is
received into the GRF.
7
CmdRst
Command reset
received
When CmdRst is set, the receiver has been sent a quadlet write
request addressed to the RESET_START CSR register.
8–10
Reserved
Reserved
Reserved
11
ITStk
Transmitter is stuck
(IT)
When ITStk is set, the transmitter has detected invalid data at the
isochronous transmit-FIFO interface.
12
ATStk
Transmitter is stuck
(AT)
When ATStk is set, the transmitter has detected invalid data at the
asynchronous transmit-FIFO interface. If the first quadlet of a packet
is not written to the ATF_First or ATF_First&Update, the transmitter
enters a state denoted by an ATStuck interrupt. An underflow of the
ATF also causes an ATStuck interrupt. If this state is entered, no
asynchronous packets can be sent until the ATF is cleared by way of
the CLR ATF control bit. Isochronous packets can be sent while in this
state.
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