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參數(shù)資料
| 型號： | TSB12C01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 10/59頁 |
| 文件大小： | 275K |
| 代理商： | TSB12C01APZ |
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1–4
1.4
Terminal Functions
Phy Interface
D0 – D7
CTL0
CTL1
LREQ
ISO
SCLK
DATA0 – DATA31
ADDR0 – ADDR7
CS
CA
WR
INT
CYCLEIN
CYCLEOUT
BCLK
RESET
RAMEz
NTCLK
NTOUT
NTBIHIZ
VCC
GND
Host
Bus
10
20
TSB12C01A
CYST
CYDNE
GRFEMP
POWERON
Figure 1–1. TSB12C01A Terminal Functions
Table 1–1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Host Bus Interface
ADDR0 –
ADDR7
22–25
27–30
I
Address 0 through address 7. Host bus address bus bits 0 through 7 that address
the quadlet-aligned FIFOs and configuration registers. The two least significant
address lines, 6 and 7, must be grounded.
CA
35
O
Cycle acknowledge (active low). CA is a TSB12C01A control signal to the host bus.
When asserted (low), access to the configuration registers or FIFO is complete.
CS
34
I
Cycle start (active low). CS is a host bus control signal to enable access to the
configuration registers or FIFO.
DATA0 –
DATA31
2–5
7–10
12–15
17–20
82–85
87–90
92–95
97–100
I/O
Data 0 through 31. DATA is a host bus data bus bits 0 through 31.
INT
37
O
Interrupt (active low). When INT is asserted (low), the TSB12C01A notifies the host
bus that an interrupt has occurred.
WR
36
I
Read/write enable. When WR is deasserted (high) in conjunction with CS, a read
from the TSB12C01A is requested. When WR is asserted (low) in conjunction with
CS, a write to the TSB12C01A is requested.
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相關代理商/技術參數(shù) |
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| TSB12C01AWN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:High-Speed Serial-Bus Link-Layer Controller |
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