參數(shù)資料
型號(hào)： TSB12C01APZ
廠商： Texas Instruments, Inc.
英文描述： High-Speed Serial-Bus Link-Layer Controller
中文描述： 高速串行總線鏈路層控制器
文件頁(yè)數(shù)： 52/59頁(yè)
文件大小： 275K
代理商： TSB12C01APZ
7–4
7.5.2
For fair or priority access, the TSB12C01A requests control of the bus at least one clock after the
TSB12C01A phy interface becomes idle CTL0 – CTL1 = 00, which indicates the physical layer is in an idle
state. If the TSB12C01A senses that CTL0 – CTL1 = 10, then it knows that its request has been lost. This
is true any time during or after the TSB12C01A sends the bus request transfer. Additionally, the phy interface
ignores any fair or priority requests when it asserts the receive state while the TSB12C01A is requesting
the bus. The link then reissues the request one clock after the next interface idle.
Bus Request
The cycle master uses a normal priority request to send a cycle-start message. After receiving a cycle start,
the TSB12C01A can issue an isochronous bus request. When arbitration is won, the TSB12C01A proceeds
with the isochronous transfer of data. The isochronous request is cleared in the phy interface once the
TSB12C01A sends another type of request or when the isochronous transfer has been completed.
The TakeBus request is issued when the TSB12C01A needs to send an acknowledgment after reception
of a packet addressed to it. This request must be issued during packet reception. This is done to minimize
the delay times that a phy interface would have to wait between the end of a packet reception and the
transmittal of an acknowledgment. As soon as the packet ends, the phy interface immediately grants access
of the bus to the TSB12C01A. The TSB12C01A sends an acknowledgment to the sender unless the header
CRC of the packet turns out to be invalid. In this case, the TSB12C01A releases the bus immediately; it is
not allowed to send another type of packet on this grant. To ensure this, the TSB12C01A is forced to wait
160 ns after the end of the packet is received. The phy interface then gains control of the bus and the
acknowledge with the CRC error sent. The bus is then released and allowed to proceed with another
request.
Although highly improbable, it is conceivable that two separate nodes believe that an incoming packet is
intended for them. The nodes then issue a TakeBus request before checking the CRC of the packet. Since
both phys seize control of the bus at the same time, a temporary, localized collision of the bus occurs
somewhere between the competing nodes. This collision would be interpreted by the other nodes on the
network as being a ZZ line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken
node drops its request and the false line state is removed. The only side effect is the loss of the intended
acknowledgment packet (this is handled by the higher layer protocol).
7.5.3
When the TSB12C01A requests to read the specified register contents, the phy interface sends the contents
of the register to the TSB12C01A through a status transfer. When an incoming packet is received while the
phy interface is transferring status information to the TSB12C01A, the phy interface continues to attempt
to transfer the contents of the register until it is successful.
Read/Write Requests
For write requests, the phy interface loads the data field into the appropriately addressed register as soon
as the transfer has been completed. The TSB12C01A is allowed to request read or write operations at any
time.
See Section 7.6, for a more detailed description of the status transfer.
7.6
Status
A status transfer is initiated by the phy interface when it has some status information to transfer to the
TSB12C01A. The transfer is initiated by asserting the following: CTL0 – CTL1 = 01 and D0 – D1 are used
to transmit the status data; see Table 7–9 for status-request functions. D2 – D7 are not used for status
transfers.
The status transfer can be interrupted by an incoming packet from another node. When this occurs, the phy
interface attempts to resend the status information after the packet has been acted upon. The phy interface
continues to attempt to complete the transfer until the information has been successfully transmitted.
NOTE:
There must be at least one idle cycle between consecutive status transfers.
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