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參數(shù)資料
| 型號： | TSB12C01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 23/59頁 |
| 文件大?。?/td> | 275K |
| 代理商： | TSB12C01APZ |
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3–7
Table 3–4. Interrupt- and Mask-Register Field Descriptions (Continued)
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
13
Reserved
Reserved
Reserved
14
SntRj
Busy acknowledge
sent by receiver
When SntRj is set, the receiver is forced to send a busy acknowledge
to a packet addressed to this node because the GRF overflowed.
15
HdrEr
Header error
When HdrEr is set, the receiver detected a header CRC error on an
incoming packet that may have been addressed to this node.
16
TCErr
Transaction code
error
When TCErr is set, the transmitter detected an invalid transaction code
in the data at the transmit FIFO interface.
17–19
Reserved
Reserved
Reserved
20
CySec
Cycle second
incremented
When CySec is set, the cycle-second field in the cycle-timer register
is incremented. This occurs approximately every second when the
cycle timer is enabled.
21
CySt
Cycle started
When CySt is set, the transmitter has sent or the receiver has received
a cycle-start packet.
22
CyDne
Cycle done
When CyDne is set, an arbitration gap has been detected on the bus
after the transmission or reception of a cycle-start packet. This
indicates that the isochronous cycle is over.
23
CyPnd
Cycle pending
When CyPnd is set, the cycle-timer offset is set to 0 (rolled over or
reset) and remains set until the isochronous cycle ends.
24
CyLst
Cycle lost
When CyLst is set, the cycle timer has rolled over twice without the
reception of a cycle-start packet. This occurs only when this node is not
the cycle master.
25
CArbFI
Cycle arbitration
failed
When CArbFI is set, the arbitration to send the cycle-start packet failed.
26–30
Reserved
Reserved
Reserved
31
IArbFI
Isochronous
arbitration failed
When IArbFI is set, the arbitration to send an isochronous packet failed.
3.2.5
The cycle-timer register contains the seconds_count, cycle_count and cycle_offset fields of the cycle timer.
The register is at address 14h and is read/write. This field is controlled by the cycle master, cycle source,
and cycle timer enable bits of the control register. Its initial value is 0000_0000h.
Cycle-Timer Register
Table 3–5. Cycle-Timer Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0–6
seconds_count
Seconds count
1-Hz cycle-timer counter
7–19
cycle_count
Cycle count
8,000-Hz cycle-timer counter
20–31
cycle_offset
Cycle offset
24.576-MHz cycle-timer counter
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