參數(shù)資料
型號(hào)： TSB12C01APZ
廠商： Texas Instruments, Inc.
英文描述： High-Speed Serial-Bus Link-Layer Controller
中文描述： 高速串行總線鏈路層控制器
文件頁(yè)數(shù)： 20/59頁(yè)
文件大?。?/td> 275K
代理商： TSB12C01APZ
3–4
Table 3–3. Control-Register Field Descriptions (Continued)
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
2–4
BsyCtrl
Busy control
These bits control which busy status (as described in IEEE 1394-1995
standard, the chip returns to incoming packets. The field is defined as
follows:
000 = follow normal busy/retry protocol, only send busy when
necessary.
001 = send busyA when it is necessary to send a busy acknowledge.
010 = send busyB when it is necessary to send a busy
acknowledge.
011 = reserved
100 = send a busy acknowledge to all incoming packets following the
normal busy/retry protocol.
101 = send a busy acknowledge to all incoming packets by sending
a busyA acknowledge.
110 = send a busy acknowledge to all incoming packets by sending
a busyB acknowledge.
111 = reserved
When retry_X is received and the receiving node needs to send a busy
acknowledge signal, it sends an ack_busy_X signal.
5
TxEn
Transmitter enable
When TxEn is cleared, the transmitter does not arbitrate or send
packets.
6
RxEn
Receiver enable
When RXEn is cleared, the receiver does not receive any packets.
7
PSBz
Physical DMA
busy
When:
1) PSOn is set,
2) PSRO is cleared or the incoming packet is a read,
3) destination offset is in the lower 4 Gbytes, and
4) PSBz is set,
the TSB12C01A sends a busy acknowledge to the incoming packet.
8
PSOn
Physical DMA on
When PSOn is set, the TSB12C01A uses PSRO and PSBz to determine
acceptance of incoming request packets addressed to the lower
4 Gbytes of initial memory space.
9
PSRO
Physical DMA read
only
When PSOn is set, the TSB12C01A uses PSRO to determine the
acceptance of incoming write request packets addressed to the lower
4 Gbytes of initial memory space.
10
RstTx
Reset transmitter
When RstTx is set, the entire transmitter resets synchronously. This bit
clears itself.
11
RstRx
Reset receiver
When RstRx is set, the entire receiver resets synchronously. This bit
clears itself.
12–15
BlkBusDep
Block bus-
dependent
address
This field is used by the receiver to filter out broadcast packets to the
bus-dependent area of CSR space. Setting the LSB of this field disables
the reception of broadcast packets to the lowest 128 bytes of
bus-dependent CSR space. Setting the MSB of this field disables the
reception of broadcast packets to the highest 128 bytes of
bus-dependent CSR space.
16–17
ATRC
AT retry code
This field contains the last retry code received. This code is logically
ORed with the retry code field (00) in the transmit packet, and the packet
is resent. This alleviates the need to change the retry code in the transmit
packet. The retry encoding follows the IEEE 1394-1995 standard. The
retry code is as follows:
00
retry_o (new)
10
retry_A
01
11
retry_X
retry_B
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TSB12C01AWN 制造商:TI 制造商全稱:Texas Instruments 功能描述:High-Speed Serial-Bus Link-Layer Controller
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