參數(shù)資料
型號(hào)： TMP20F2810PBKAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 53/159頁
文件大?。?/td> 2084K
代理商： TMP20F2810PBKAEP
Functional Overview
53
March 2004 Revised October 2004
SGUS051A
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is
the WATCHDOG.
3.12
Low-Power Modes Block
The low-power modes on the F281x and C281x are similar to the 240x devices. Table 316 summarizes the
various modes.
Table 316. F281x and C281x Low-Power Modes
MODE
LPM(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT
Normal
X,X
on
on
on
IDLE
0,0
on
on
on
XRS,
WDINT,
Any Enabled Interrupt,
XNMI
Debugger§
STANDBY
0,1
on
(watchdog still running)
off
off
XRS,
WDINT,
XINT1
,
XNMI
,
T1/2/3/4CTRIP
,
C1/2/3/4/5/6TRIP
,
SCIRXDA,
SCIRXDB,
CANRX,
Debugger§
HALT
1,X
off
(oscillator and PLL turned off,
watchdog not functional)
off
off
XRS,
XNMI
,
Debugger§
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not
be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional
while on the 24x/240x the clock is turned off.
§On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is
recognized by the processor. The LPM block performs no tasks during
this mode as long as the LPMCR0(LPM) bits are set to 0,0.
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
Only the XRS and XNMI external signals can wake the device from
HALT mode. The XNMI input to the core has an enable/disable bit.
Hence, it is safe to use the XNMI signal for this function.
STANDBY Mode:
HALT Mode:
NOTE:
The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them in when the IDLE instruction was executed.
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