參數(shù)資料
型號(hào): TMP20F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 102/159頁
文件大小: 2084K
代理商: TMP20F2810PBKAEP
Electrical Specifications
102
March 2004 Revised October 2004
SGUS051A
tw(RSL)
th(XPLLDIS)
GPIOF14/XF (User-Code Dependent)
th(XMP/MC)
tOSCST
VDDIO, VDD3VFL
VDDAn, VDDAIO
(3.3 V)
XCLKIN
X1
XRS
XF/XPLLDIS
XMP/MC
VDD, VDD1 (1.8 V (or
1.9 V))
I/O Pins
XPLLDIS Sampling
Address/Data/
Control
XCLKOUT
(Don’t Care)
(Don’t Care)
XCLKIN/8 (See Note A)
(Don’t Care)
Input Configuration (State Depends on Internal PU/PD)
User-Code Dependent
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
User-Code Dependent
2.5 V
0.3 V
td(EX)
NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V..
See Note B
tsu(XPLLDIS)
Figure 610. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
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