參數(shù)資料
型號(hào)： TMP20F2810PBKAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 125/159頁
文件大小： 2084K
代理商： TMP20F2810PBKAEP
Electrical Specifications
124
March 2004 Revised October 2004
SGUS051A
6.24
External Interface Read Timing
Table 627. External Memory Interface Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
th(XA)XRD
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 628. External Memory Interface Read Timing Requirements
Delay time, XCLKOUT high to zone chip-select active low
1
ns
Delay time, XCLKOUT high/low to zone chip-select inactive high
2
3
ns
Delay time, XCLKOUT high to address valid
2
ns
Delay time, XCLKOUT high/low to XRD active low
1
ns
Delay time, XCLKOUT high/low to XRD inactive high
2
1
ns
Hold time, address valid after zone chip-select inactive high
ns
Hold time, address valid after XRD inactive high
ns
MIN
MAX
UNIT
ta(A)
ta(XRD)
tsu(XD)XRD
th(XD)XRD
LR = Lead period, read access. AR = Active period, read access. See Table 625.
Access time, read data from address valid
(LR + AR) 14
AR 12
ns
Access time, read data valid from XRD active low
ns
Setup time, read data valid before XRD strobe inactive high
12
ns
Hold time, read data valid after XRD inactive high
0
ns
Lead
Active
Trail
DIN
td(XCOHL-XRDL)
td(XCOH-XA)
td(XCOH-XZCSL)
td(XCOHL-XRDH)
th(XD)XRD
td(XCOHL-XZCSH)
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
tsu(XD)XRD
ta(A)
ta(XRD)
XREADY
Figure 629. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
N/A
XWRACTIVE
N/A
XWRTRAIL
N/A
READYMODE
N/A
≥
1
≥
0
≥
0
0
0
N/A = “Don’t care” for this example
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