參數(shù)資料
型號(hào)： TMP20F2810PBKAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 100/159頁
文件大?。?/td> 2084K
代理商： TMP20F2810PBKAEP
Electrical Specifications
100
March 2004 Revised October 2004
SGUS051A
6.14.2
Output Clock Characteristics
Table 68. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
No.
PARAMETER
MIN
6.67§
TYP
MAX
UNIT
C1
tc(XCO)
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
Cycle time, XCLKOUT
ns
C3
Fall time, XCLKOUT
2
ns
C4
Rise time, XCLKOUT
2
ns
C5
Pulse duration, XCLKOUT low
H2
H+2
ns
C6
Pulse duration, XCLKOUT high
PLL lock time
H2
H+2
ns
C7
131072tc(CI)
ns
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
§The PLL must be used for maximum frequency operation.
This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
C4
C3
XCLKOUT
(see Note B)
XCLKIN
C5
C9
C10
C1
C8
C6
(see Note A)
NOTES: A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 68 is
intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 68. Clock Timing
6.15
Reset Timing
Table 69. Reset (XRS) Timing Requirements
MIN
NOM
MAX
UNIT
tw(RSL1)
Pulse duration, stable XCLKIN to XRS high
8tc(CI)
8tc(CI)
cycles
tw(RSL2)
Pulse duration, XRS low
Warm reset
cycles
WD-initiated reset
512tc(CI)
512tc(CI)
32tc(CI)
tw(WDRS)
td(EX)
tOSCST
Pulse duration, reset pulse generated by watchdog
cycles
Delay time, address/data valid after XRS high
cycles
Oscillator start-up time
1
10
ms
tsu(XPLLDIS)
Setup time for XPLLDIS pin
16tc(CI)
cycles
th(XPLLDIS)
Hold time for XPLLDIS pin
16tc(CI)
cycles
th(XMP/MC)
Hold time for XMP/MC pin
16tc(CI)
2520tc(CI)§
cycles
th(boot-mode)
If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
§The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320F28x Boot
ROM Reference Guide
(literature number SPRU095) and
TMS320F28x System Control and Interrupts Reference Guide
(literature number
SPRU078) for further information.
Hold time for boot-mode pins
cycles
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