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參數(shù)資料
| 型號(hào)： | TMP20F2810PBKAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 19/159頁(yè) |
| 文件大?。?/td> | 2084K |
| 代理商： | TMP20F2810PBKAEP |
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Introduction
19
March 2004 Revised October 2004
SGUS051A
Table 22. Signal Descriptions
(Continued)
NAME
DESCRIPTION
PU/PD§
I/O/Z
PIN NO.
176-PIN
PGF
128-PIN
PBK
179-PIN
GHH
XINTF SIGNALS (2812 ONLY) (CONTINUED)
XREADY
B6
161
I
PU
Ready Signal. Indicates peripheral is ready to complete the
access when asserted to 1. XREADY can be configured to be
a synchronous or an asynchronous input. See the timing
diagrams for more details.
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
K9
77
58
I
Oscillator Input input to the internal oscillator. This pin is also
used to feed an external clock. The 28x can be operated with
an external clock source, provided that the proper voltage
levels be driven on the X1/XCLKIN pin. It should be noted that
the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core
digital power supply (VDD), rather than the 3.3-V I/O supply
(VDDIO). A clamping diode may be used to clamp a buffered
clock signal to ensure that the logic-high level does not
exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
Oscillator Output
X2
M9
76
57
O
XCLKOUT
F11
119
87
O
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose clock
source. XCLKOUT is either the same frequency, 1/2 the
frequency, or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be
turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register
to 1.
TESTSEL
A13
134
97
I
PD
Test Pin. Reserved for TI. Must be connected to ground.
XRS
D6
160
113
I/O
PU
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution.
The PC will point to the address contained at the location
0x3FFFC0. When XRS is brought to a high level, execution
begins at the location pointed to by the PC. This pin is driven
low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS pin will be driven low for the
watchdog reset duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal
pullup (100
μ
A, typical). It is recommended that this pin be
driven by an open-drain device.
TEST1
M7
67
51
I/O
Test Pin. Reserved for TI. On F281x devices, TEST1 must be
left unconnected. On C281x devices, this pin is a “no connect
(NC)” (i.e., this pin is not connected to any circuitry internal
to the device).
TEST2
N7
66
50
I/O
Test Pin. Reserved for TI. On F281x devices, TEST2 must be
left unconnected. On C281x devices, this pin is a “no connect
(NC)” (i.e., this pin is not connected to any circuitry internal
to the device).
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§PU = pin has internal pullup; PD = pin has internal pulldown
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