參數(shù)資料
型號： TMP20F2810PBKAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 27/159頁
文件大?。?/td> 2084K
代理商： TMP20F2810PBKAEP
Functional Overview
27
March 2004 Revised October 2004
SGUS051A
3.1
Memory Map
Block
Start Address
íííííííííííí
íííííííííííí
XINTF Zone 7 (16K
×
16, XZCS6AND7)
(Enabled if MP/MC = 1)
íííííííííííí
íííííííííííí
íííííííííííí
íííííííííííí
XINTF Zone 1 (8K
×
16, XZCS0AND1) (Protected)
íííííííííííííííííííííí
íííííííííííííííííííííí
ííííííííííí
(Enabled if MP/MC = 0)
íííííííííííííííííííííí
íííííííííííííííííííííí
ííííííííííí
íííííííííííííííííííííí
íííííííííííííííííííííí
íííííííííííííííííííííí
Reserved (1K)
íííííííííííííííííííííí
ííííííííííí
íííííííííííííííííííííí
L
(
0x00 0000
M0 Vector RAM (32
×
32)
(Enabled if VMAP = 0)
Data Space
Prog Space
M0 SARAM (1K
×
16)
M1 SARAM (1K
×
16)
ííííííííííííííííí
ííííííííííííííííí
ííííííííííííííííí
Reserved
Peripheral Frame 0
(2K
×
16)
PIE Vector - RAM
(256
×
16)
(Enabled if VMAP
0x00 0040
0x00 0400
0x00 0800
íííííííííííííííííííííí
Reserved
L0 SARAM (4K
×
16, Secure Block)
Peripheral Frame 1
ííííííííííííííííí
ííííííííííííííííí
ííííííííííííííííí
Reserved
Peripheral Frame 2
(4K
×
16, Protected)
L1 SARAM (4K
×
16, Secure Block)
Reserved
Flash (or ROM) (128K
×
16, Secure Block)
128-Bit Password
H0 SARAM (8K
×
16)
Reserved
BROM Vector - ROM (32
×
32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
0x00 0D00
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
0x3D 7C00
0x3D 8000
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
H
(
P
Reserved
XINTF Zone 2 (0.5M
×
16, XZCS2)
XINTF Vector - RAM (32
×
32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
On-Chip Memory
External Memory XINTF
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
LEGEND:
0x08 0000
0x00 4000
0x10 0000
0x18 0000
0x3F C000
0x00 2000
íííííííííííííííííííííí
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 32. F2812/C2812 Memory Map (See Notes A through E)
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