參數(shù)資料
型號: TMP20F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號處理器
文件頁數(shù): 118/159頁
文件大小: 2084K
代理商: TMP20F2810PBKAEP
Electrical Specifications
117
March 2004 Revised October 2004
SGUS051A
6.21
SPI Slave Mode Timing
Table 623. SPI Slave Mode External Timing (Clock Phase = 0)
NO.
12
MIN
MAX
UNIT
ns
tc(SPC)S
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Cycle time, SPICLK
4tc(LCO)
0.5tc(SPC)S10
0.5tc(SPC)S10
0.5tc(SPC)S10
0.5tc(SPC)S10
13§
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
14§
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
15§
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
0.375tc(SPC)S10
ns
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S10
16§
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75tc(SPC)S
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75tc(SPC)S
19§
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
ns
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
20§
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S
ns
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LS4
(SPIBRR
tc(LCO) = LSPCLK cycle time
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
or
LSPCLK
1)
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