參數(shù)資料
型號: TMP20F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號處理器
文件頁數(shù): 48/159頁
文件大?。?/td> 2084K
代理商: TMP20F2810PBKAEP
Functional Overview
48
March 2004 Revised October 2004
SGUS051A
3.7
System Control
This section describes the F281x and C281x oscillator, PLL and clocking mechanisms, the watchdog function
and the low power modes. Figure 38 shows the various clock and reset domains in the F281x and C281x
devices that will be discussed.
HSPCLK
PLL
X1/XCLKIN
X2
Power
Modes
Control
Watchdog
Block
C28x
CPU
P
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
Peripheral
Registers
High-Speed Peripherals
EV-A/B
High-Speed Prescaler
Low-Speed Prescaler
Clock Enables
GPIO
MUX
System
Control
Registers
Peripheral
Registers
XF_XPLLDIS
ADC
Registers
12-Bit ADC
16 ADC Inputs
HSPCLK
LSPCLK
I/O
I/O
Peripheral Reset
SYSCLKOUT
XRS
Reset
GPIOs
eCAN
Peripheral
Registers
I/O
OSC
CLKIN
NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
(See Note A)
Figure 38. Clock and Reset Domains
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