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| 型號： | TMP20F2810PBKAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 130/159頁 |
| 文件大小： | 2084K |
| 代理商： | TMP20F2810PBKAEP |
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Electrical Specifications
129
March 2004 Revised October 2004
SGUS051A
6.27
External Interface Ready-on-Write Timing With One External Wait State
Table 634. External Memory Interface Write Switching Characteristics
(Ready-on-Write, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
td(XWEL-XD)
th(XA)XZCSH
th(XD)XWE
tdis(XD)XRNW
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access (see Table 625)
Delay time, XCLKOUT high to zone chip-select active low
1
ns
Delay time, XCLKOUT high or low to zone chip-select inactive high
2
3
ns
Delay time, XCLKOUT high to address valid
2
ns
Delay time, XCLKOUT high/low to XWE low
2
ns
Delay time, XCLKOUT high/low to XWE high
2
ns
Delay time, XCLKOUT high to XR/W low
1
ns
Delay time, XCLKOUT high/low to XR/W high
2
1
ns
Enable time, data bus driven from XWE low
0
ns
Delay time, data valid after XWE active low
4
ns
Hold time, address valid after zone chip-select inactive high
ns
Hold time, write data valid after XWE inactive high
TW2
ns
Data bus disabled after XR/W inactive high
4
ns
Table 635. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
§
MIN
MAX
UNIT
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
te(XRDYsynchH)
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
§The first XREADY (Synch) sample occurs with respect to E in Figure 633:
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE +n 1) tc(XTIM) tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
Hold time, XREADY (Synch) low
12
ns
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
3
ns
Setup time, XREADY (Synch) high before XCLKOUT high/low
15
ns
Hold time, XREADY (Synch) held high after zone chip select high
0
ns
Table 636. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
MIN
MAX
UNIT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
te(XRDYasynchH)
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
The first XREADY (Synch) sample occurs with respect to E in Figure 634:
E = (XWRLEAD + XWRACTIVE 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE 3 + n) tc(XTIM) tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Asynch) low before XCLKOUT high/low
11
ns
Hold time, XREADY (Asynch) low
8
ns
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
3
ns
Setup time, XREADY (Asynch) high before XCLKOUT high/low
11
ns
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
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