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| 型號： | TCP pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU) |
| 中文描述： | 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器） |
| 文件頁數(shù)： | 6/49頁 |
| 文件大小： | 947K |
| 代理商： | TCP PENTIUM PROCESSOR |
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PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
Figure 1 shows a block diagram of the Pentium
processor.
6
The block diagram shows the two instruction
pipelines, the "u" pipe and "v" pipe. The u-pipe can
execute all integer and floating point instructions. The
v-pipe can execute simple integer instructions and
the FXCH floating-point instructions.
The separate caches are shown, the code cache and
data cache. The data cache has two ports, one for
each of the two pipes (the tags are triple ported to
allow simultaneous inquire cycles). The data cache
has a dedicated Translation Lookaside Buffer (TLB)
to translate linear addresses to the physical
addresses used by the data cache.
The code cache, branch target buffer and prefetch
buffers are responsible for getting raw instructions
into the execution units of the Pentium processor.
Instructions are fetched from the code cache or from
the external bus. Branch addresses are remembered
by the branch target buffer. The code cache TLB
translates linear addresses to physical addresses
used by the code cache.
The decode unit decodes the prefetched instructions
so the Pentium processor can execute the
instruction. The control ROM contains the microcode
which controls the sequence of operations that must
be performed to implement the Pentium processor
architecture. The control ROM unit has direct control
over both pipelines.
The Pentium processors contain a pipelined floating-
point unit that provides a significant floating-point
performance advantage over previous generations of
processors.
The architectural features introduced in this section
are more fully described in the Pentium
Processor
Family Developer's Manual, Volume 3
3.0.
TCP PINOUT
3.1.
Pentium Processor with
Voltage Reduction Technology
Differences from the SPGA
3.3V Pentium Processor
To better streamline the part for mobile applications,
the following features have been eliminated from the
TCP and SPGA Pentium processor with voltage
reduction technology: Upgrade, Dual Processing
(DP), APIC and Master/Checker functional
redundancy. Table 1 lists the corresponding pins
which exist on the SPGA 3.3V Pentium processor
but have been removed on the TCP and SPGA
Pentium processor with voltage reduction
technology.
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