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參數資料
| 型號： | TCP pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU with 64-Bit Data Bus(帶64位數據總線32位CPU) |
| 中文描述： | 32位與64位數據總線（帶64位數據總線32位的CPU中央處理器） |
| 文件頁數： | 21/49頁 |
| 文件大小： | 947K |
| 代理商： | TCP PENTIUM PROCESSOR |
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E
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
21
Table 4. Quick Pin Reference (Contd.)
Symbol
Type
Name and Function
SMI#
I
The
system management interrupt
causes a system management interrupt
request to be latched internally. When the latched SMI# is recognized on an
instruction boundary, the processor enters System Management Mode.
SMIACT#
O
An active
system management interrupt active
output indicates that the
processor is operating in System Management Mode.
STPCLK#
I
Assertion of the
stop clock
input signifies a request to stop the internal clock of the
Pentium processor with voltage reduction technology thereby causing the core to
consume less power. When the CPU recognizes STPCLK#, the processor will stop
execution on the next instruction boundary, unless superseded by a higher priority
interrupt, and generate a Stop Grant Acknowledge cycle. When STPCLK# is
asserted, the processor will still respond to external snoop requests.
TCK
I
The
testability clock
input provides the clocking function for the processor
boundary scan in accordance with the IEEE Boundary Scan interface (Standard
1149.1). It is used to clock state information and data into and out of the processor
during boundary scan.
TDI
I
The
test data input
is a serial input for the test logic. TAP instructions and data are
shifted into the processor on the TDI pin on the rising edge of TCK when the TAP
controller is in an appropriate state.
TDO
O
The
test data output
is a serial output of the test logic. TAP instructions and data
are shifted out of the processor on the TDO pin on TCK's falling edge when the TAP
controller is in an appropriate state.
TMS
I
The value of the
test mode select
input signal sampled at the rising edge of TCK
controls the sequence of TAP controller state changes.
TRST#
I
When asserted, the
test reset
input allows the TAP controller to be asynchronously
initialized.
V
CC
2
I
These pins are the 2.9V power inputs to the Pentium processor with voltage
reduction technology.
V
CC
3
I
These pins are the 3.3V power inputs to the Pentium processor with voltage
reduction technology.
V
SS
I
These pins are the ground inputs to the Pentium processor with voltage reduction
technology.
W/R#
O
Write/read
s one of the primary bus cycle definition pins. It is driven valid in the
same clock as the ADS# signal is asserted. W/R# distinguishes between write and
read cycles.
WB/WT#
I
The
writeback/writethrough
input allows a data cache line to be defined as
writeback or writethrough on a line-by-line basis. As a result, it determines whether
a cache line is initially in the S or E state in the data cache.
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