參數(shù)資料
型號: TCP pentium processor
廠商: Intel Corp.
英文描述: 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述: 32位與64位數(shù)據(jù)總線(帶64位數(shù)據(jù)總線32位的CPU中央處理器)
文件頁數(shù): 26/49頁
文件大小: 947K
代理商: TCP PENTIUM PROCESSOR
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
26
4.0.
TCP PENTIUM PROCESSOR
ELECTRICAL SPECIFICATIONS
4.1.
Maximum Ratings
The following values are stress ratings only.
Functional operation at the maximum ratings is not
implied
nor
guaranteed.
conditions are given in the AC and DC specification
tables.
Functional
operating
Extended exposure to the maximum ratings may
affect device reliability. Furthermore, although the
Pentium processor with voltage reduction technology
contains protective circuitry to resist damage from
static electric discharge, always take precautions to
avoid high static voltages or electric fields.
Case temperature under bias______
65
°
C to 110
°
C
Storage temperature_____________
65
°
C to 150
°
C
3V Supply voltage
with respect to V
SS
______________
0.5V to +4.6V
2.9V Supply voltage
with respect to V
SS
______________
0.5V to +4.1V
3V Only Buffer DC Input
Voltage ________________________
0.5V to V
CC
3
_________________________
+0.5; not to exceed 4.6V
(2)
5V Safe Buffer
DC Input Voltage _____________
0.5V to 6.5V
(1,3)
NOTES:
1.
Applies to CLK.
2.
Applies to all Pentium processors with voltage
reduction technology inputs except CLK.
3.
See Table 10.
WARNING
Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only.
Operation beyond the "Operating Conditions"
is not recommended and extended exposure
beyond the "Operating Conditions" may affect
device reliability.
4.2.
DC Specifications
Tables 9, 10 and 11 list the DC specifications which
apply to the TCP Pentium processor with voltage
reduction technology. The Pentium processor with
voltage reduction technology core operates at 2.9V
internally while the I/O interface operates at 3.3V.
The CLK input may be 3.3V or 5V. Since the 3.3V
(5V safe) input levels defined in Table 10
are the
same as the 5V TTL levels, the CLK input is
compatible with existing 5V clock drivers. The power
dissipation specification in Table 12 is provided for
design of thermal solutions during operation in a
sustained maximum level. This is the worst-case
power the device would dissipate in a system for a
sustained period of time. This number is used for
design of a thermal solution for the device.
4.2.1.
POWER SEQUENCING
There is no specific sequence required for powering
up or powering down the V
2 and V
3 power
supplies. However, for compatibility with future
mobile processors, it is recommended that the V
2
and V
3 power supplies be either both on or both
off within one second of each other.
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