參數(shù)資料
型號(hào)： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁(yè)數(shù)： 17/49頁(yè)
文件大?。?/td> 947K
代理商： TCP PENTIUM PROCESSOR
E
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
17
Table 4. Quick Pin Reference (Contd.)
Symbol
Type
Name and Function
BRDY#
I
The
burst ready
input indicates that the external system has presented valid data
on the data pins in response to a read or that the external system has accepted the
processor data in response to a write request. This signal is sampled in the T2, T12
and T2P bus states.
BREQ
O
The
bus request
output indicates to the external system that the processor has
internally generated a bus request. This signal is always driven whether or not the
processor is driving its bus.
BUSCHK#
I
The
bus check
input allows the system to signal an unsuccessful completion of a
bus cycle. If this pin is sampled active, the processor will latch the address and
control signals in the machine check registers. If, in addition, the MCE bit in CR4 is
set, the processor will vector to the machine check exception.
CACHE#
O
For processor-initiated cycles, the
cache
pin indicates internal cacheability of the
cycle (if a read), and indicates a burst writeback cycle (if a write). If this pin is driven
inactive during a read cycle, the processor will not cache the returned data,
regardless of the state of the KEN# pin. This pin is also used to determine the cycle
length (number of transfers in the cycle).
CLK
I
The
clock
input provides the fundamental timing for the processor. Its frequency is
the operating frequency of the processor external bus and requires TTL levels. All
external timing parameters except TDI, TDO, TMS, TRST# and PICD0-1 are
specified with respect to the rising edge of CLK.
NOTE:
It is recommended that CLK begin 150 ms after V
reaches its proper operating
level. This recommendation is only to assure the long term reliability of the device.
D/C#
O
The
data/code
output is one of the primary bus cycle definition pins. It is driven
valid in the same clock as the ADS# signal is asserted. D/C# distinguishes between
data and code or special cycles.
D63-D0
I/O
These are the 64
data lines
for the processor. Lines D7-D0 define the least
significant byte of the data bus; lines D63-D56 define the most significant byte of the
data bus. When the CPU is driving the data lines, they are driven during the T2, T12
or T2P clocks for that cycle. During reads, the CPU samples the data bus when
BRDY# is returned.
DP7-DP0
I/O
These are the
data parity
pins for the processor. There is one for each byte of the
data bus. They are driven by the processor with even parity information on writes in
the same clock as write data. Even parity information must be driven back to the
Pentium processor with voltage reduction technology on these pins in the same
clock as the data to ensure that the correct parity check status is indicated by the
processor. DP7 applies to D63-D56; DP0 applies to D7-D0.
EADS#
I
This signal indicates that a valid
external address
has been driven onto the
processor address pins to be used for an inquire cycle.
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