參數(shù)資料
型號： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁數(shù)： 18/49頁
文件大小： 947K
代理商： TCP PENTIUM PROCESSOR
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
18
Table 4. Quick Pin Reference (Contd.)
Symbol
Type
Name and Function
EWBE#
I
The
external write buffer empty
input, when inactive (high), indicates that a write
cycle is pending in the external system. When the processor generates a write and
EWBE# is sampled inactive, the processor will hold off all subsequent writes to all
E- or M-state lines in the data cache until all write cycles have completed, as
indicated by EWBE# being active.
FERR#
O
The
floating point error
pin is driven active when an unmasked floating point error
occurs. FERR# is similar to the ERROR# pin on the Intel387 math coprocessor.
FERR# is included for compatibility with systems using DOS-type floating point
error reporting.
FLUSH#
I
When asserted, the
cache flush
input forces the processor to write back all
modified lines in the data cache and invalidate its internal caches. A Flush
Acknowledge special cycle will be generated by the processor indicating completion
of the writeback and invalidation.
NOTE:
If FLUSH# is sampled low when RESET transitions from high to low, tristate test
mode is entered.
HIT#
O
The
hit
indication is driven to reflect the outcome of an inquire cycle. If an inquire
cycle hits a valid line in either the data or instruction cache, this pin is asserted two
clocks after EADS# is sampled asserted. If the inquire cycle misses the cache, this
pin is negated two clocks after EADS#. This pin changes its value only as a result
of an inquire cycle and retains its value between the cycles.
HITM#
O
The
hit to a modified line
output is driven to reflect the outcome of an inquire
cycle. It is asserted after inquire cycles which resulted in a hit to a modified line in
the data cache. It is used to inhibit another bus master from accessing the data until
the line is completely written back.
HLDA
O
The
bus hold acknowledge
pin goes active in response to a hold request driven to
the processor on the HOLD pin. It indicates that the processor has floated most of
the output pins and relinquished the bus to another local bus master. When leaving
bus hold, HLDA will be driven inactive and the processor will resume driving the
bus. If the processor has a bus cycle pending, it will be driven in the same clock
that HLDA is de-asserted.
HOLD
I
In response to the
bus hold request
, the processor will float most of its output and
input/output pins and assert HLDA after completing all outstanding bus cycles. The
processor will maintain its bus in this state until HOLD is de-asserted. HOLD is not
recognized during LOCK cycles. The processor will recognize HOLD during reset.
IERR#
O
The
internal error
pin is used to indicate internal parity errors. If a parity error
occurs on a read from an internal array, the processor will assert the IERR# pin for
one clock and then shutdown.
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