參數(shù)資料
型號(hào)： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁(yè)數(shù)： 4/49頁(yè)
文件大小： 947K
代理商： TCP PENTIUM PROCESSOR
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
2.1.
Mobile Pentium
Processor
Family Architecture
4
The application instruction set of the Pentium
processor family includes the complete Intel486 CPU
family
instruction
set
accommodate some of the additional functionality of
the Pentium processors. All application software
written for the Intel386 and Intel486 family
microprocessors will run on the Pentium processors
without
modification.
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of CPUs.
with
extensions
to
The
on-chip
memory
The
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one clock,
or one floating point instruction (under certain
circumstances, two floating-point instructions) in one
clock.
Pentium
processors
implement
several
Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch code
in a linear fashion, and one that prefetches code
according to the Branch Target Buffer (BTB) so the
needed code is almost always prefetched before it is
needed for execution.
The
redesigned over the Intel486 CPU. Faster algorithms
provide up to 10X speed-up for common operations
including add, multiply and load.
floating-point
unit
has
been
completely
Pentium processors include separate code and data
caches integrated on-chip to meet performance
goals. Each cache is 8 Kbytes in size, with a 32-byte
line size and is 2-way set associative. Each cache
has a dedicated Translation Lookaside Buffer (TLB)
to translate linear addresses to physical addresses.
The data cache is configurable to be writeback or
writethrough on a line-by-line basis and follows the
MESI protocol. The data cache tags are triple-ported
to support two data transfers and an inquire
cycle in the same clock. The code cache is an
inherently write-protected cache. The code cache
tags are also triple ported to support snooping and
split line accesses. Individual pages can be
configured as cacheable or non-cacheable by
software or hardware. The caches can be enabled or
disabled by software or hardware.
The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate. Burst
read and burst writeback cycles are supported by the
Pentium processors. In addition, bus cycle pipelining
has been added to allow two bus cycles to be in
progress simultaneously. The Pentium processors'
MMU contains optional extensions to the architecture
which allow 2-Mbyte and 4-Mbyte page sizes.
The Pentium processors have added significant data
integrity and error detection capability. Data parity
checking is still supported on a byte-by-byte basis.
Address parity checking and internal parity checking
features have been added along with a new
exception, the machine check exception.
As more and more functions are integrated on chip,
the complexity of board level testing is increased. To
address this, the Pentium processors have increased
test and debug capability. The Pentium processors
implement IEEE Boundary Scan (Standard 1149.1).
In addition, the Pentium processors have specified
four breakpoint pins that correspond to each of the
debug registers and externally indicate a breakpoint
match.
Execution
tracing
indications when an instruction has completed
execution in either of the two internal pipelines, or
when a branch has been taken.
provides
external
System Management Mode (SMM) has been
implemented along with some extensions to the SMM
architecture. Enhancements to the virtual 8086 mode
have been made to increase performance by
reducing the number of times it is necessary to trap
to
a
virtual
8086
monitor.
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