參數(shù)資料
型號(hào)： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁(yè)數(shù)： 20/49頁(yè)
文件大?。?/td> 947K
代理商： TCP PENTIUM PROCESSOR
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
20
Table 4. Quick Pin Reference (Contd.)
Symbol
Type
Name and Function
NA#
I
An active
next address
input indicates that the external memory system is ready to
accept a new bus cycle although all data transfers for the current cycle have not yet
completed. The processor will issue ADS# for a pending cycle two clocks after NA#
is asserted. The processor supports up to two outstanding bus cycles.
NMI
I
The
non-maskable interrupt
request signal indicates that an external non-
maskable interrupt has been generated.
PCD
O
The
page cache disable
pin reflects the state of the PCD bit in CR3; Page
Directory Entry or Page Table Entry. The purpose of PCD is to provide an external
cacheability indication on a page-by-page basis.
PCHK#
O
The
parity check
output indicates the result of a parity check on a data read. It is
driven with parity status two clocks after BRDY# is returned. PCHK# remains low
one clock for each clock in which a parity error was detected. Parity is checked only
for the bytes on which valid data is returned.
PEN#
I
The
parity enable
input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle. If
this pin is sampled active in the clock, a data parity error is detected. The processor
will latch the address and control signals of the cycle with the parity error in the
machine check registers. If, in addition, the machine check enable bit in CR4 is set
to "1", the processor will vector to the machine check exception before the
beginning of the next instruction.
PM/BP[1:0]
O
These pins function as part of the performance monitoring feature.
The breakpoint 1-0 pins are multiplexed with the
performance monitoring 1-0
pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.
PRDY
O
The
probe ready
output pin indicates that the processor has stopped normal
execution in response to the R/S# pin going active or Probe Mode being entered.
PWT
O
The
page writethrough
pin reflects the state of the PWT bit in CR3, the page
directory entry, or the page table entry. The PWT pin is used to provide an external
writeback indication on a page-by-page basis.
R/S#
I
The
run / stop
input is an asynchronous, edge-sensitive interrupt used to stop the
normal execution of the processor and place it into an idle state. A high to low
transition on the R/S# pin will interrupt the processor and cause it to stop execution
at the next instruction boundary.
RESET
I
RESET
forces the processor to begin execution at a known state. All the processor
internal caches will be invalidated upon the RESET. Modified lines in the data cache
are not written back. FLUSH# and INIT are sampled when RESET transitions from
high to low to determine if tristate test mode will be entered or if BIST will be run.
SCYC
O
The
split cycle
output is asserted during misaligned LOCKed transfers to indicate
that more than two cycles will be locked together. This signal is defined for locked
cycles only. It is undefined for cycles which are not locked.
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