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| 型號： | TCP pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU) |
| 中文描述： | 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器） |
| 文件頁數(shù)： | 47/49頁 |
| 文件大小： | 947K |
| 代理商： | TCP PENTIUM PROCESSOR |
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E
4.4.
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
47
I/O Buffer Models
This section describes the I/O buffer models of the
Pentium
processor
with
technology.
voltage
reduction
The first order I/O buffer model is a simplified
representation of the complex input and output
buffers used in the Pentium processor with voltage
reduction technology. Figures 10 and 11 show the
structure of the input buffer model and Figure 12
shows the output buffer model. Tables 16 and 17
show the parameters used to specify these models.
Although simplified, these buffer models will
accurately model flight time and signal quality. For
these parameters, there is very little added accuracy
in a complete transistor model.
The following two models represent the input buffer
models. The first model, Figure 10, represents all of
the input buffers except for a special group of input
buffers. The second model, Figure 11, represents
these special buffers. These buffers are the inputs:
AHOLD, EADS#, KEN#, WB/WT#, INV, NA#,
EWBE#, BOFF# and CLK.
In addition to the input and output buffer parameters,
input protection diode models are provided for added
accuracy. These diodes have been optimized to
provide ESD protection and provide some level of
clamping. Although the diodes are not required for
simulation, it may be more difficult to meet
specifications without them.
Note, however, some signal quality specifications
require that the diodes be removed from the input
model. The series resistors (Rs) are a part of the
diode model. Remove these when removing the
diodes from the input model.
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