參數(shù)資料
型號(hào)： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁(yè)數(shù)： 34/49頁(yè)
文件大?。?/td> 947K
代理商： TCP PENTIUM PROCESSOR
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
34
Table 13. Mobile Pentium
Processor AC Specifications for 50-MHz Bus Operation (Contd.)
VCC2 = 2.9V ±165mV, VCC3 = 3.3V ±165mV, TCP TCASE = 0
°
C to 95
°
C, SPGA TCASE = 0
°
C to 85
°
C, CL = 0 pF
Symbol
Parameter
Min
Max
Unit
Figure
Notes
t
56
All Non-Test Outputs Float Delay
25.0
nS
8
(1), (3), (8), (10)
t
57
All Non-Test Inputs Setup Time
5.0
nS
8
(3), (7), (10)
t
58
All Non-Test Inputs Hold Time
13.0
nS
8
(3), (7), (10)
4.3.5.
AC TIMINGS FOR A 60-MHZ BUS
The AC specifications given in Table 14 consists of
output delays, input setup requirements and input
hold requirements for the 60-MHz external bus. All
AC specifications (with the exception of those for the
TAP signals and APIC
signals) are relative to the rising edge of the CLK
input.
All timings are referenced to 1.5V for both "0" and "1"
logic levels unless otherwise specified. Within the
sampling window, a synchronous input must be
stable for correct operation.
Table 14. Mobile Pentium
Processor with Voltage Reduction Technology
AC Specifications for 60-MHz Bus Operation
VCC2 = 2.9V ±165mV, VCC3 = 3.3V ±165mV, TCP TCASE = 0
°
C to 95
°
C, SPGA TCASE = 0
°
C to 85
°
C, CL = 0 pF
Symbol
Parameter
Min
Max
Unit
Figure
Notes
Frequency
30.0
60.0
MHz
t
1a
CLK Period
16.67
33.33
nS
3
t
1b
CLK Period Stability
±
250
pS
(1), (19)
t
2
CLK High Time
4.0
nS
3
@2V, (1)
t
3
CLK Low Time
4.0
nS
3
@0.8V, (1)
t
4
CLK Fall Time
0.15
1.5
nS
3
(2.0V–0.8V),
(1), (5)
t
5
CLK Rise Time
0.15
1.5
nS
3
(0.8V–2.0V),
(1), (5)
t
6a
ADS#, PWT, PCD, BE0-7#, M/IO#,
D/C#, CACHE#, SCYC, W/R#
Valid Delay
1.0
7.0
nS
4
(22)
t
6b
AP Valid Delay
1.0
8.5
nS
4
(22)
t
6c
LOCK# Valid Delay
1.1
7.0
nS
4
(22)
t
6e
A3-A31 Valid Delay
1.1
6.3
nS
4
(22)
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