參數(shù)資料
型號(hào)： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁(yè)數(shù)： 29/49頁(yè)
文件大?。?/td> 947K
代理商： TCP PENTIUM PROCESSOR
E
4.3.
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
29
AC Specifications
The AC specifications of the TCP Pentium processor
with voltage reduction technology consist of setup
times, hold times, and valid delays at 0 pF. All TCP
Pentium processor with voltage reduction technology
AC specifications are valid for V
2 = 2.9V ±165mV,
V
CC
3 = 3.3V ±165mV and Tcase = 0 to 95°C.
WARNING
Do not exceed the 75-MHz Pentium processor
with voltage reduction technology internal
maximum frequency of 75 MHz by either
selecting the 1/2 bus fraction or providing a
clock greater than 50 MHz.
Do not exceed the 90-MHz Pentium processor
with voltage reduction technology internal
maximum frequency of 90 MHz by either
selecting the 1/2 bus fraction or providing a
clock greater than 60 MHz.
4.3.1.
POWER AND GROUND
For clean on-chip power distribution, the TCP
Pentium processor with voltage reduction technology
has 37 V
CC
2 (2.9V power), 42 V
3 (3.3V power)
and 72 V
(ground) inputs. Power and ground
connections must be made to all external V
2, V
CC3
and V
pins of the Pentium processor with voltage
reduction technology. On the circuit board all V
2
pins must be connected to a 2.9V V
plane (or
island) and all V
3 pins must be connected to a
3.3V V
3 plane. All V
pins must be connected to
a V
SS
plane. Please refer to Table 2 for the list of
V
CC
CC
3 and V
SS
pins.
4.3.2.
DECOUPLING RECOMMENDATIONS
Transient power surges can occur as the processor
is executing instruction sequences or driving large
loads. To mitigate these high frequency transients,
liberal high frequency decoupling capacitors should
be placed near the processor.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance can be reduced by
shortening circuit board traces
processor and decoupling capacitors as much as
possible.
between
the
These capacitors should be evenly distributed
around each component on the 3.3V plane and the
2.9V plane (or island). Capacitor values should be
chosen to ensure they eliminate both low and high
frequency noise components.
Power transients also occur as the processor rapidly
transitions from a low level of power consumption to
a much higher level (or high to low power). A typical
example would be entering or exiting the Stop Grant
state. Another example would be executing a HALT
instruction, causing the processor to enter the Auto
HALT Powerdown state, or transitioning from HALT
to the Normal state. All of these examples may cause
abrupt changes in the power being consumed by the
processor. Note that the Auto HALT Powerdown
feature is always enabled even when other power
management features are not implemented.
Bulk storage capacitors with a low ESR (Effective
Series Resistance) in the 10 to 100 μf range are
required to maintain a regulated supply voltage
during the interval between the time the current load
changes and the point that the regulated power
supply output can react to the change in load. In
order to reduce the ESR, it may be necessary to
place several bulk storage capacitors in parallel.
These capacitors should be placed near the
processor (on the 3.3V plane and the 2.9V plane (or
island)) to ensure that these supply voltages stay
within specified limits during changes in the supply
current during operation.
For more detailed information, please contact Intel or
refer to the Pentium
Processor with Voltage
Reduction Technology: Power Supply Design
Considerations for Mobile Systemsapplication note
(Order Number 242558).
4.3.3.
CONNECTION SPECIFICATIONS
All NC pins must remain unconnected.
For reliable operation, always connect unused inputs
to an appropriate signal level. Unused active low
inputs should be connected to V
3. Unused active
high inputs should be connected to ground.
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