參數(shù)資料
型號(hào)： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁(yè)數(shù)： 19/49頁(yè)
文件大?。?/td> 947K
代理商： TCP PENTIUM PROCESSOR
E
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
19
Table 4. Quick Pin Reference (Contd.)
Symbol
Type
Name and Function
IGNNE#
I
This is the
ignore numeric error
input. This pin has no effect when the NE bit in
CR0 is set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the
processor will ignore any pending unmasked numeric exception and continue
executing floating-point instructions for the entire duration that this pin is asserted.
When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked numeric
exception exists (SW.ES = 1), and the floating-point instruction is one of FINIT,
FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the
processor will execute the instruction in spite of the pending exception. When the
CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked numeric exception
exists (SW.ES = 1), and the floating-point instruction is one other than FINIT,
FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the
processor will stop execution and wait for an external interrupt.
INIT
I
The processor
initialization
input pin forces the processor to begin execution in a
known state. The processor state after INIT is the same as the state after RESET
except that the internal caches, write buffers, and floating point registers retain the
values they had prior to INIT. INIT may NOT be used in lieu of RESET after power
up.
If INIT is sampled high when RESET transitions from high to low, the processor will
perform built-in self test prior to the start of program execution.
INTR
I
An active
maskable interrupt
input indicates that an external interrupt has been
generated. If the IF bit in the EFLAGS register is set, the processor will generate
two locked interrupt acknowledge bus cycles and vector to an interrupt handler after
the current instruction execution is completed. INTR must remain active until the
first interrupt acknowledge cycle is generated to assure that the interrupt is
recognized.
INV
I
The
invalidation
input determines the final cache line state (S or I) in case of an
inquire cycle hit. It is sampled together with the address for the inquire cycle in the
clock EADS# is sampled active.
KEN#
I
The
cache enable
pin is used to determine whether the current cycle is cacheable
or not and is consequently used to determine cycle length. When the processor
generates a cycle that can be cached (CACHE# asserted) and KEN# is active, the
cycle will be transformed into a burst line fill cycle.
LOCK#
O
The
bus lock
pin indicates that the current bus cycle is locked. The processor will
not allow a bus hold when LOCK# is asserted (but AHOLD and BOFF# are
allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes
inactive after the BRDY# is returned for the last locked bus cycle. LOCK# is
guaranteed to be de-asserted for at least one clock between back-to-back locked
cycles.
M/IO#
O
The
memory/input-output
is one of the primary bus cycle definition pins. It is
driven valid in the same clock as the ADS# signal is asserted. M/IO# distinguishes
between memory and I/O cycles.
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