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| 型號： | TCP pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU) |
| 中文描述： | 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器） |
| 文件頁數(shù)： | 28/49頁 |
| 文件大?。?/td> | 947K |
| 代理商： | TCP PENTIUM PROCESSOR |
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PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
Table 11. Input and Output Characteristics
28
Symbol
Parameter
Min
Max
Unit
Notes
C
IN
Input Capacitance
15
pF
(4)
C
O
Output Capacitance
20
pF
(4)
C
I/O
I/O Capacitance
25
pF
(4)
C
CLK
CLK Input Capacitance
15
pF
(4)
C
TIN
Test Input Capacitance
15
pF
(4)
C
TOUT
Test Output Capacitance
20
pF
(4)
C
TCK
Test Clock Capacitance
15
pF
(4)
I
LI
Input Leakage Current
±
15
μ
A
0 < V
IN
< V
CC
3
(1)
I
LO
Output Leakage Current
±
15
μ
A
0 < V
IN
< V
CC
3
(1)
I
IH
Input Leakage Current
200
μ
A
V
IN
= 2.4V (3)
I
IL
Input Leakage Current
400
μ
A
V
IN
= 0.4V (2)
NOTES:
1.
2.
3.
4.
This parameter is for input without pull up or pull down.
This parameter is for input with pull up.
This parameter is for input with pull down.
Guaranteed by design.
Table 12. Power Dissipation Requirements for Thermal Solution Design
Parameter
Typical
(1)
Max
(2)
Unit
Notes
Active Power Dissipation
2.0–3.0
2.5–3.5
2.8–3.9
6.0
7.3
8.0
Watts
Watts
Watts
@75 MHz
@90 MHz
@100 MHz (5)
Stop Grant and Auto Halt
Powerdown Power Dissipation
1.0
1.2
1.3
Watts
Watts
Watts
@75 MHz (3)
@90 MHz (3)
@100 MHz (3)
Stop Clock Power Dissipation
.02
0.05
Watts
(4)
NOTES:
1.
This is the typical power dissipation in a system. This value was the average value measured in a system using a typical
device at V
2 = 2.9V and V
CC
3 = 3.3V running typical applications. This value is highly dependent upon the specific
system configuration.
Systems must be designed to thermally dissipate the maximum active power dissipation. It is determined using a worst-
case instruction mix with V
2 = 2.9V and V
CC
3 = 3.3V. The use of nominal V
CC
in this measurement takes into account
the thermal time constant of the package.
Stop Grant/Auto Halt Powerdown Power Dissipation is determined by asserting the STPCLK# pin or executing the HALT
instruction.
Stop Clock Power Dissipation is determined by asserting the STPCLK# pin and then removing the external CLK input.
Refer to document 242557 for new process specification.
2.
3.
4.
5.
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