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| 型號： | TCP pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU) |
| 中文描述： | 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器） |
| 文件頁數(shù)： | 41/49頁 |
| 文件大小： | 947K |
| 代理商： | TCP PENTIUM PROCESSOR |
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E
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
41
Table 15. Mobile Pentium Processor AC Specifications for 66-MHz Bus Operation (Contd.)
VCC2 = 2.9V ±165mV, VCC3 = 3.3V ±165mV, TCP TCASE = 0
°
C to 95
°
C, SPGA TCASE = 0
°
C to 85
°
C, CL = 0 pF
Symbol
Parameter
Min
Max
Unit
Figure
Notes
t
43a
BF, CPUTYP Setup Time
1.0
mS
7
(18) to RESET
falling edge
t
43b
BF, CPUTYP Hold Time
2.0
CLKs
7
(18) to RESET
falling edge
t
43c
APICEN, BE4# Setup Time
2.0
CLKs
7
To RESET falling
edge
t
43d
APICEN, BE4# Hold Time
2.0
CLKs
7
To RESET falling
edge
t
44
TCK Frequency
—
16.0
MHz
t
45
TCK Period
62.5
nS
3
t
46
TCK High Time
25.0
nS
3
@2V, (1)
t
47
TCK Low Time
25.0
nS
3
@0.8V, (1)
t
48
TCK Fall Time
5.0
nS
3
(2.0V–0.8V), (1),
(8), (9)
t
49
TCK Rise Time
5.0
nS
3
(0.8V–2.0V), (1),
(8), (9)
t
50
TRST# Pulse Width
40.0
nS
9
(1), Asynchronous
t
51
TDI, TMS Setup Time
5.0
nS
8
(7)
t
52
TDI, TMS Hold Time
13.0
nS
8
(7)
t
53
TDO Valid Delay
3.0
20.0
nS
8
(8)
t
54
TDO Float Delay
25.0
nS
8
(1), (8)
t
55
All Non-Test Outputs Valid Delay
3.0
20.0
nS
8
(3), (8), (10)
t
56
All Non-Test Outputs Float Delay
25.0
nS
8
(1), (3), (8), (10)
t
57
All Non-Test Inputs Setup Time
5.0
nS
8
(3), (7), (10)
t
58
All Non-Test Inputs Hold Time
13.0
nS
8
(3), (7), (10)
NOTES:
Notes 2, 6 and 14 are general and apply to all standard TTL signals used with the Pentium
1.
Not 100 percent tested. Guaranteed by design.
2.
TTL input test waveforms are assumed to be 0 to 3V transitions with 1V/nS rise and fall times.
3.
Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These
timings correspond to the response of these signals due to boundary scan operations.
4.
APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition
without false transitions (i.e., glitches).
5.
0.8V/ns
≤
CLK input rise/fall time
≤
8V/ns.
6.
0.3V/ns
≤
input rise/fall time
≤
5V/ns.
7.
Referenced to TCK rising edge.
processor family.
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