參數(shù)資料
型號(hào)： TCP pentium processor
廠商： Intel Corp.
英文描述： 32-Bit CPU with 64-Bit Data Bus(帶64位數(shù)據(jù)總線32位CPU)
中文描述： 32位與64位數(shù)據(jù)總線（帶64位數(shù)據(jù)總線32位的CPU中央處理器）
文件頁(yè)數(shù)： 16/49頁(yè)
文件大小： 947K
代理商： TCP PENTIUM PROCESSOR
PENTIUM
PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
E
16
Table 4. Quick Pin Reference
Symbol
Type
Name and Function
A20M#
I
When the
address bit 20 mask
pin is asserted, the Pentium
address wraparound at 1 Mbyte which occurs on the 8086. When A20M# is asserted,
the processor masks physical address bit 20 (A20) before performing a lookup to the
internal caches or driving a memory cycle on the bus. The effect of A20M# is
undefined in protected mode. A20M# must be asserted only when the processor is in
real mode.
processor emulates the
A31-A3
I/O
As outputs, the
address
lines of the processor along with the byte enables define the
physical area of memory or I/O accessed. The external system drives the inquire
address to the processor on A31-A5.
ADS#
O
The
address status
indicates that a new valid bus cycle is currently being driven by
the processor.
AHOLD
I
In response to the assertion of
address hold
, the processor will stop driving the
address lines (A31-A3), and AP in the next clock. The rest of the bus will remain
active so data can be returned or driven for previously issued bus cycles.
AP
I/O
Address parity
is driven by the processor with even parity information on all
processor generated cycles in the same clock that the address is driven. Even parity
must be driven back to the processor during inquire cycles on this pin in the same
clock as EADS# to ensure that correct parity check status is indicated.
APCHK#
O
The
address parity check
status pin is asserted two clocks after EADS# is sampled
active if the processor has detected a parity error on the address bus during inquire
cycles. APCHK# will remain active for one clock each time a parity error is detected.
BE7#-BE5#
BE4#-BE0#
O
I/O
The
byte enable
pins are used to determine which bytes must be written to external
memory, or which bytes were requested by the CPU for the current cycle. The byte
enables are driven in the same clock as the address lines (A31-3).
BF
I
Bus Frequency
determines the bus-to-core ratio. BF is sampled at RESET, and
cannot be changed until another non-warm (1 ms) assertion of RESET. Additionally,
BF must not change values while RESET is active. For proper operation of the
processor, this pin should be strapped high or low. When BF is strapped to V
, the
processor will operate at a 2/3 bus/core frequency ratio. When BF is strapped to V
SS
,
the processor will operate to a 1/2 bus/core frequency ratio. If BF is left floating, the
processor defaults to a 2/3 bus/core ratio.
BOFF#
I
The
backoff
input is used to abort all outstanding bus cycles that have not yet
completed. In response to BOFF#, the processor will float all pins normally floated
during bus hold in the next clock. The processor remains in bus hold until BOFF# is
negated, at which time the Pentium processor restarts the aborted bus cycle(s) in
their entirety.
BP[3:2]
PM/BP[1:0]
O
The
breakpoint
pins (BP3-0) correspond to the debug registers, DR3-DR0. These
pins externally indicate a breakpoint match when the debug registers are
programmed to test for breakpoint matches.
BP1 and BP0 are multiplexed with the
performance monitoring
pins (PM1 and
PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come out
of RESET configured for performance monitoring.
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