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| 型號(hào)： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 91/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
87
Questions and Answers
(continued)
U-Interface
(continued)
Q26:
How can proprietary messages be passed across
the U-interface
A26:
The embedded operations channel (EOC) pro-
vides one way of doing this. ANSI standard
T1.601 defines 64 8-bit messages which can be
used for nonstandard applications. They range in
value from binary 00010000 to 01000000.
There is also a provision for sending bulk data
over the EOC. Setting the data/message indicator
bit to 0 indicates the current 8-bit EOC word con-
tains data that is to be passed transparently with-
out being acted on. Note that there is no
response time requirement placed on the NT in
this case (i.e., the NT does not have to echo the
message back to the LT). Also note that this is
currently only an ANSI provision and is not an
ANSI requirement. The T7256 does support this
provision.
Q27:
What is the value of the ANSI T1.601 cso and nib
bits in the 2B1Q frame
A27:
cso and nib are fixed at 0 and 1, respectively, by
the device. This is because the device always has
warm start capability (CSO = 0), and NT1s are
required to have nib = 1 per T1.601-1992.
Q28:
Are the PS bits controllable from outside the
chip
A28:
Yes, the bits are controlled by two pins (8 and 9)
on the chip. When the T7256 TDM highway is
enabled, these pins change function and become
part of the TDM highway and PS1 and PS2 are
controlled by register GR1, bits 1 and 2.
Q29:
It looks like the U-interface sai and act bits that
the T7256 transmits towards the LT always track
one another. If this is the case, I don’t understand
why they are both needed. Can you explain the
purpose of the sai bit and how it relates to the act
bit
A29:
The sai bit is equal to 1 when there is activity
(INFO 1 or INFO 3) on the S/T-interface. The act
bit is 1 whenever layer 1 transparency is estab-
lished. Most of the time these bits are the same,
but there are two situations where they will be dif-
ferent.
1. The sai bit can be used in conjunction with the
uoa bit from the LT to support DSL-only activa-
tion as described in the ANSI and ETSI stan-
dards. The LT can request a U-only activation
by setting uoa = 0, which will cause the
S/T-interface to remain in a deactivated state.
If the TE requests an activation under these
conditions by transmitting INFO 1 to the
T7256, the sai bit will change from 0 to 1,
indicating to the LT that there is activity on the
S/T-interface so that the LT can respond
accordingly. Typically, this means that LT will
set uoa = 1 to exit the DSL-only condition so
that layer-1 transparency can be established
from TE to LT. Thus, in the case of a DSL-only
activation, the T7256's sai bit is 1 and its act bit
is 0 from the time a TE requests an activation
until the following events occur:
A. LT sets uoa = 1 towards the NT.
B. The T7256 detects uoa = 1 and transmits
INFO 2 on the S/T-interface.
C. The TE synchronizes and transmits INFO 3
on the S/T-interface.
D. Upon reception of the INFO 3 signal, the
T7256 sets act = 1.
2. If a link is fully active, then the LT detects a
transition of the NT act bit from 1 to 0, it is an
indication of loss of layer-1 transparency. This
can be caused by either a) S/T loss of sync or
b) NT1 received INFO 0. Case a) will result in
an act = 0/sai = 1 combination, i.e., S/T sync is
lost but there is still activity on the S/T-inter-
face, meaning the TE is having trouble staying
synchronized. Case b) will result in an act =
0/sai = 0 combination, i.e., no activity on the
S/T-interface (INFO 0), meaning the TE has
been disconnected (there is no way the TE can
legally send INFO 0 when the link is fully active
because the TE is not allowed to initiate deac-
tivation—only the LT is—so the only other pos-
sibility is that it has been disconnected or has
failed). Note that this procedure allows the CO
to determine whether the cause of loss of layer
1 transparency is a TE that is having synchro-
nization problems or a TE that has been dis-
connected, based on the state of the sai bit
when act = 0.
The ANSI T1.601 and ETSI ETR 080 stan-
dards contain finite state matrices that de-
scribe DSL-only operation. The T7256 follows
the behavior described in the matrices. Refer
to those tables for detailed information on each
of the states.
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