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| 型號(hào)： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 67/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
63
Application Briefs
(continued)
Interfacing the T7256 to the Motorola
68302
(continued)
Using the Motorola MC68302 PCM Mode to Interface
to the T7256 TDM Highway
In PCM mode, any number of the MC68302 internal
SCCs can be multiplexed to support a TDM type of
interface (see Section 4.4.3, PCM Highway Mode in the
MC68302 Data Book). The SCCs in PCM mode require
a data-in lead (L1RXD) for receive data, a data-out
lead (L1TXD) for transmit data, and a common receive
and transmit data clock to clock data into and out of the
SCCs (L1CLK). These signals are directly compatible
with the T7256 TDM highway. In addition, the PCM-
mode SCCs require two data synchronization signals,
L1SY1 and L1SY0, which route specific TDM time slots
to the SCCs. These signals are not directly supported
by T7256, and some glue logic is required to generate
them.
The L1SY0/1 signal pair combinations are used to
select between PCM channels 1, 2, and 3 (or to select
no PCM channel), where each channel is routed to one
of the SCCs (routing is controlled by software). They
can be set up in an envelope mode such that the they
are active for N bits, where N determines the number of
bits in a time slot. Values of N equal to 7 and 8 are
required to interface to the T7256 TDM highway B-
channel time slots (for 56 kbits/s or 64 kbits/s data,
respectively). A value of N equal to 2 is required to
interface to the D-channel time slots. Table 32 lists the
L1SY0/1 channel assignments for the T7256-to-
MC68302 interface circuit.
Table 32. PCM Channel Selection
The interface circuit can be easily implemented in a
programmable logic device. An example is presented
here using the Altera* EPM7032 EPLD. The EPM7032
was selected for this example because it is used on the
SCNT1 Family Reference Design Board (SCNT1-RDB)
to implement this same function, so the design files
presented here have already been proven on an actual
hardware platform (consult Appendix B, SCNT1 Family
Reference Design Board Hardware User Manual,
MN96-011ISDN, for detailed design information). The
design uses 43% of the EPM7032, which leaves a
large portion of the device available for other glue func-
tions that may be required. If no other system glue is
required, the design can be ported to a smaller,
cheaper EPLD.
The inputs to the circuit from the T7256 are FS, TDM-
CLK, and CKOUT (CKOUT must be programmed to a
frequency of 10 MHz via register GR0, bits 2—1 in
order for the circuit to operate properly). The inputs to
the circuit from the 68302 are PA0 and PA1 (parallel
port A, bits 0 and 1), which are used to control the 7-bit
envelope mode on the B1 and B2 channels. These two
signals are called 7BIT_B1 and 7BIT_B2 in the design
files and, when set high, enable the 7-bit time-slot
mode (otherwise, 8-bit time-slot mode is active). The
outputs from the circuit are L1SY0 and L1SY1, which
drive the corresponding signals on the 68302.
The design was implemented using the Altera
MAX+plus II development system. Figures 24, 25, 26,
and 27 illustrate the circuit schematic, Altera high-level
design language (AHDL) files, and the timing diagrams
for the design.
* Altera is a registered trademark of Altera Corporation.
L1SY0
0
1
L1SY1
0
0
Channel Accessed
None
PCM Channel 1
(U-interface B1 channel)
PCM Channel 2
(U-interface B2 channel)
PCM Channel 3
(U-interface D channel)
0
1
1
1
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