- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T7234A Compliance with the New ETSI PSD Requirement PDF資料下載
參數(shù)資料
| 型號(hào)： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 103/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁當(dāng)前第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
99
Questions and Answers
(continued)
S/T-Interface
(continued)
Q37:
What is the state of the D-echo bit during an EOC
2B+D loopback
A37:
The D-echo bit (SXE, GR2, bit 3) should be set to
zero to meet the ITU-T I.430 requirement in
Appendix I, Note 4, which states that during a
loopback 2 (eoc 2B+D loopback), the NT1 should
send INFO 4 frames toward the TE with the D-
echo channel bits set binary zero. If AUTOEOC =
1 (register GRO, bit 4), SXE is internally overrid-
den to 0 by the T7256. If AUTOEOC = 0, SXE
must be set to 0 by the user.
Q38:
Is it possible to make a nontransparent single B-
channel loopback toward the S/T-interface via the
microprocessor
A38:
Yes. Refer to the data sheet for a description of
the ITU-T I.430 Loop C loopback control bits (reg-
ister DFRO).
Q39:
What is the purpose of the SFECV bit in register
SIR0
A39:
ANSI T1 T1.605 Table 6, “Codes for Q-Channel
and SC1-Subchannel Messages,” defines an
SC1-Subchannel message, “Far-End Code Viola-
tion” (SC11, SC12, SC13, SC14 = 1110). This is
an S-channel message that the NT can send to
the TE to indicate that a previous multiframe
received by the NT contains one or more illegal
S/T line code violations. In an NT1 that supports
multiframing, the SFECV bit can be used to gen-
erate an interrupt to the T7256 microprocessor
indicating that it should transmit the “Far-End
Code Violation” message to the TE in S-subchan-
nel one. This subchannel is accessed via register
MCR1 bits 0—3.
Q40:
In the Analog Interface section of the S/T-inter-
face description in the data sheet, where does
the value of 0 ms—3.1 ms maximum differential
delay in adaptive timing mode come from
A40:
The minimum value of 0 ms is necessary so that
the NT's transmitter and receiver can be directly
connected in a loopback and still synchronize.
The maximum value of 3.1 ms comes about
because the window size needed in the adaptive
timing algorithm is 2.1 ms. The window size is the
time during each bit period in which no transitions
may occur. Since a period is 5.2 ms, the time dur-
ing which there may be transitions is
5.2 ms – 2.1 ms, or 3.1 ms. This is the same as
the maximum differential delay, since the earliest
and latest bit transitions represent the nearest
and farthest TEs relative to the NT receiver.
Miscellaneous
Q41:
Is the
±
100 ppm free-run frequency recommen-
dation met in the T7256
A41:
In the free-run mode, the output frequency is pri-
marily dependent on the crystal, not the silicon
design. For low-cost crystals, initial tolerance,
temperature, and aging effects may account for
two-thirds of this budget, and just a couple of pF
of variation in load capacitance will use up the
rest; therefore, the
±
100 ppm goal can be met if
the crystal parameters are well controlled. See
the Crystal Characteristics section in this data
sheet.
Q42:
What happens if Co and Cm of the crystal differs
from the specification shown in the Crystal Char-
acteristics table
A42:
None of the parameters should be varied. We
have not characterized any such crystals, and
have no easy method of doing so. A crystal
whose parameters deviate from the requirements
may work in most applications but fail in isolated
cases involving certain loop configurations or
other system variations. Therefore, customers
choosing to vary any of these parameters do so
at their own risk.
Q43:
It has been noted in some other designs that the
crystal has a capacitor from each pin to ground.
Changing these capacitances allows the fre-
quency to be adjusted to compensate for board
parasitics. Can this be done with the T7256 crys-
tal Also, can we use a crystal from our own
manufacturer
A43:
For the T7256, these capacitors are located on
the chip, so their values are fixed. The advantage
to this is that no external components are
required. The disadvantage is that board parasit-
ics must be very small.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7237A | Compliance with the New ETSI PSD Requirement |
| T7256A | Compliance with the New ETSI PSD Requirement |
| T7288 | CEPT/E1 Line Interface(CEPT/E1 線接口) |
| T7290A | DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口) |
| T7295-1 | E3 Integrated Line Receiver(E3 集成線接收器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7237 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7240 | 制造商:TE Connectivity 功能描述: |
| T7-241A5 | 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
| T7-241B1 | 制造商:OTTO 功能描述:Toggle Switches ON NONE ON 2 Pole Standard Bat Handle 制造商:OTTO Engineering Inc 功能描述:Switch Toggle ON None ON DPDT Bat Toggle PC Pins 16A 115VAC 28VDC PC Mount with Threads |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。