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參數(shù)資料
| 型號(hào)： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 45/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
41
Microprocessor Interface Description
(continued)
Timing
(continued)
For microprocessors using a multiplexed data out/in pin
to drive SDI and SDO (as shown in Figure 13), a read
instruction to T7256 will require that the microproces-
sor data in/out pin be an output during the command/
address byte written to T7256, and then switch to an
input to read the data byte T7256 presents on the SDO
pin in response to the read command. In this case, the
microprocessor data in/out pin must 3-state within
1.46
μ
s of the final SCK rising edge of the command/
address byte to ensure that there is no contention
between the microprocessor data out pin and the
T7256 SDO pin.
Time-Division Multiplexed (TDM) Bus
Description
The TDM bus facilitates B1-, B2-, and D-channel com-
munication between the T7256 and peripheral devices
such as codecs, HDLC processors, time-slot inter-
changers, synchronous data interfaces, etc. The follow-
ing list is a subset of the devices that can connect
directly to the T7256 TDM bus:
I
Lucent T7570 and T7513 Codecs
I
Lucent T7270 Time-Slot Interchanger
I
Lucent T7121 HDLC Formatter
I
National Semiconductor*3070 Codec
The bus can be used to extract data from S/T- or
U-interface receivers, process the data externally, and
source data to the appropriate transmitters with the
processed data. The bus can also be used to simply
monitor 2B+D channel data flow within the T7256 with-
out modifying it. The bus also supports board-level test-
ing procedures using in-circuit techniques (see the
Board-Level Testing section for more details). Upon
powerup, the TDM bus is not selected. Pins 4, 7, 8, and
9 form the TDM bus when TDMEN is set to 0 (register
GR2, bit 5).
The TDM bus consists of a 2.048 MHz output clock
(TDMCLK), data in (TDMDI), data out (TDMDO), and a
programmable frame strobe lead (FS). The frame
* National Semiconductor is a registered trademark of National
Semiconductor Corporation.
strobe timing can be configured via the microprocessor
register bits FSC and FSP in register TDR0. Data
appearing and expected on the bus is controlled via the
B1-, B2-, and D-channel data flow register bits (regis-
ters DFR0 and DFR1). The TDMCLK and FS outputs
only become active if one or more of the TDM time
slots is enabled (see register DFR1, Table 8).
Clock and Data Format
The clock and data signals for the TDM bus are
TDMCLK, TDMDO, and TDMDI (see Figure 15).
TDMCLK is a 2.048 MHz output clock. TDMDO is the
2B+D data output for data derived from either the
S/T-interface receiver, U-interface receiver, or both. The
TDMDO output driver is only active during a time slot
when it is driving data off-chip; otherwise, the output
driver is 3-stated (this includes the 6-bit interval in the
D-channel octet). TDMDI is the 2B+D data input for
data used to drive either the S/T-interface transmitter,
U-interface transmitter, or both.
On both the TDMDO and TDMDI leads, six 8-bit time
slots are reserved for the B1-, B2-, and D-channels
associated with the S/T- and U-interfaces. The relative
locations of the time slots are fixed; however, the frame
strobe is programmable. The total number of time slots
available within each frame strobe period is 32. During
unused time slots, data on TDMDI is ignored and
TDMDO is 3-stated.
Frame Strobe
The FS frame strobe is a programmable output associ-
ated with the TDM bus. FS can be configured to serve
as an envelope strobe for any of the six reserved time
slots available on the bus: U-interface B1, B2, and D
and S/T-interface B1, B2, and D. FS can also be pro-
grammed as a 2B+D envelope for either the U-interface
or S/T-interface time slots. FS can be used to directly
drive a codec for voice applications or can be used to
control other external devices such as HDLC control-
lers.
Figure 15 shows the relationship between the
TDMCLK, TDMDO, and TDMDI time slots, and the FS
strobe for some example programmable settings.
Detailed descriptions of TDM bus interface timing are
given in the Timing Characteristics section of this docu-
ment.
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