參數(shù)資料
型號： T7234A
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 110/116頁
文件大?。?/td> 1056K
代理商： T7234A
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
106
Lucent Technologies Inc.
Glossary
(continued)
ERC1:
eoc state machine control—
information register.
ESD:
Electrostatic discharge.
ETSI:
European Telecommunications
Standards Institute.
FEBE:
Far-end block error (register
CFR1, bit 5).
FSC[2:0]:
Frame strobe (FS) control,
(register TDR0, bits 2—0).
FSP:
Frame strobe (FS) polarity
(register TDR0, bit 3).
FT:
Fixed/adaptive timing control
(register GR2, bit 0).
FTE/TDMDI:
Fixed/adaptive timing mode
select.
GIR0:
Global interrupt register.
GND
A
:
Analog ground.
GND
O
:
Crystal oscillator ground.
GR0:
Global device control—device
configuration register.
GR1:
Global device control—
U-interface register.
GR2:
Global device control—
S/T-interface register.
HBM:
Human-body model.
HDLC:
High-level data link control.
HIGHZ:
High impedance control.
HN:
Hybrid
negative input for
U-interface.
HP:
Hybrid positive input for
U-interface.
I4C:
INFO 4 change (register SIR0,
bit 3).
I4CM:
INFO 4 change mask (register
SIR1, bit 3).
I4I:
INFO 4 indicator (register CFR1,
bit 7).
ILINT:
Insertion loss interrupt
(register MIR0, bit 1).
ILINTM:
Insertion loss interrupt mask
(register MIR1, bit 1).
ILOSS:
Insertion loss test control
(register CFR0, bit 0).
ILOSS:
Insertion loss test control.
ISDN:
Integrated services digital net-
work.
ITU-T:
International Telecommunication
Union-Telecommunication Sec-
tor.
I[8:1]R:
Receive eoc information
(register ECR3, bits 0—7).
I[8:1]T:
Transmit eoc information
(register ERC1, bits 0—7).
LON:
Line driver negative output for
U-interface.
LOP:
Line driver positive output for
U-interface.
LPBK:
U-interface analog loopback
(register GR1, bit 0).
MCR0:
Q-channel bits register.
MCR1:
S subchannel 1 register.
MCR2:
S subchannel 2 register.
MCR3:
S subchannel 3 register.
MCR4:
S subchannel 4 register.
MCR5:
S subchannel 5 register.
MINT:
Maintenance interrupt
(register GIR0, bit 2).
MIR0:
Maintenance interrupt register.
MIR1:
Maintenance interrupt mask
register.
MLT:
Metallic loop termination.
MULTIF:
Multiframing control (register
GR0, bit 5).
NEBE:
Near-end block error (register
CFR1, bit 4).
NTM:
NT test mode (register GR1, bit 3).
OOF:
Out of frame (register CFR1,
bit 2).
OPTOIN:
Optoisolator input.
OUSC:
Other U-interface state change
(register UIR0, bit 3).
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