參數(shù)資料
型號： T7234A
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 24/116頁
文件大?。?/td> 1056K
代理商： T7234A
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
20
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 4. Global Device Control—Device Configuration (Address 00h)
Reg
GR0
Default State
on RESET
R/W
R/W
Bit 7
Rsv.
1
Bit 6
Bit 5
MULTIF
1
Bit 4
Bit 3
Bit 2
CRATE1
1
Bit 1
CRATE0
1
Bit 0
RESET
1
AUTOACT
AUTOACT/
SCK
AUTOEOC
1
AUTOCTL
1
Register
GR0
Bit
0
Symbol
RESET
Name/Description
Reset.
Same function as external RESET pin, except the state of the AUTOACT/
SCK, ACTMODE/INT, and SYN8K_CTL/SDI pins are not checked. Assertion of
this bit halts data transmission, clears adaptive filter coefficients, resets the S/T-
interface transceiver, and sets all microprocessor register bits (except itself) to
their default state. The microprocessor must write this bit back to a 1 to bring the
T7256 out of its RESET state. During reset, the U-interface transmitter produces
0 V and the output impedance is 135
at tip and ring.
0—Reset.
1—No effect on device operation (default).
CRATE[1:0]
CKOUT Rate Control.
00—Not used.
01—10.24 MHz synchronous with U-interface (if active); otherwise, free-
running.
10—15.36 MHz free-running.
11—3-state (default).
AUTOCTL
Auto Control Enable.
Enables automatic control of ANSI maintenance and re-
served bit insertion. When AUTOCTL = 1, register CFR0 is ignored and the con-
trol flow state machine automatically controls ANSI maintenance functions and
reserved bit insertion. When AUTOCTL = 0, the microprocessor controls ANSI
maintenance functions and reserved bit insertion via register CFR0.
0—CFR0 functions controlled manually by microprocessor.
1—CFR0 functions controlled automatically.
AUTOEOC
Automatic eoc Processor Enable.
Enables eoc state machine which imple-
ments eoc processing per the ANSI standard. When AUTOEOC = 1, registers
ECR0—ECR1 are ignored. The eoc state machine only responds to addresses
000 and 111 as valid addresses.
0—eoc state machine disabled.
1—eoc state machine enabled (default).
MULTIF
Multiframing Control.
Enables the multiframing controller and allows the micro-
processor to access the S and Q channels. When disabled, multiframing is not
implemented (the NT transmits all 0s in the FA
and M bit positions and all 1s in
the S bit positions to the TE). Also, register bits 3—0 in MCR0 are forced to 1 and
register bits 3—0 in MCR1—5 are forced to 0 when multiframing is disabled.
0—Multiframing controller enabled.
1—Multiframing controller disabled (default).
GR0
2—1
GR0
3
GR0
4
GR0
5
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