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參數(shù)資料
| 型號： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 15/116頁 |
| 文件大小： | 1056K |
| 代理商： | T7234A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
11
Functional Overview
The T7256 device provides four major interfaces for
information transfer: the U-interface, the S/T-interface,
the microprocessor interface, and the time-division
multiplexed (TDM) bus interface (see Figure 1). Use of
the microprocessor and TDM bus interface is optional.
If the microprocessor and TDM interfaces aren’t
required, the T7234 SCNT1 Euro-LITE may be a more
cost-effective solution (see the T7234 SCNT1 Euro-
LITE Single-Chip NT1 Data Sheet). Similarly, if an S/T-
interface is not required, the T7237 may be a more
cost-effective solution (see the T7237 ISDN U-Interface
Transceiver Data Sheet). These devices are pin-com-
patible with the T7256, but have a reduced feature set
for cost-sensitive applications that don’t require the full
feature set of the T7256.
Routing of data between the S/T, U, and TDM inter-
faces is controlled by the data flow matrix that uses
register settings accessible via the microprocessor
port. The data flow matrix circuitry routes 2B+D infor-
mation between the appropriate interfaces, under
direction of the microprocessor register settings. Rout-
ing between the T7256 interfaces allows configurations
to support both NT1 and TA applications.
The architecture of the T7256 allows for a flexible com-
bination of automatically and manually controlled func-
tions. A control flow state machine, eoc state machine,
and multiframing controller can be independently
enabled or disabled. When enabled, these circuit
blocks automatically perform their functions while
ignoring the associated control bits in the microproces-
sor registers. When disabled, the control bits are made
available to the microprocessor for manipulation. At all
times, the status bits are available to the microproces-
sor and the 2B+D data can be routed via the data flow
matrix.
The microprocessor interface is a serial communica-
tions port consisting of input data (SDI), output data
(SDO), input clock (SCK), and an output interrupt pin
(INT). The microprocessor interface supports synchro-
nous communication between the T7256 and an inex-
pensive microprocessor with a serial port. The interrupt
is maskable via the onboard microprocessor interrupt
mask registers. The internal register set controls vari-
ous functions including information routing between
interfaces, auto-eoc processing, maintenance testing,
S/T-interface timing recovery mode, S- and Q-channel
processing, microprocessor interrupt masks, activation
of the TDM bus, and frame strobe timing.
The TDM interface consists of a TDM bus data clock
(TDMCLK), input data (TDMDI), output data (TDMDO),
and frame strobe (FS). The 2B+D data is transmitted
and received in fixed time slots on the TDM bus; how-
ever, the frame strobe output lead is programmable to
support a wide variety of devices (codecs, HDLC pro-
cessors, asynchronous interfaces) for direct connection
on the TDM bus. The TDM bus exists as a selectable
option via the microprocessor interface. When the TDM
bus is activated, pins 4, 7, 8, and 9 are reconfigured to
form the bus interface.
The eoc state machine, when enabled, automatically
performs the eoc channel functions as described in the
ANSI requirements. When disabled, control of the eoc
channel is passed to the microprocessor via the appro-
priate microprocessor register bits.
The ANSI maintenance controller can operate in
fully automatic or in fully manual mode. In automatic
mode, the device decodes and responds to mainte-
nance states according to the ANSI requirements. In
manual mode, the device is controlled by an external
maintenance decoder that drives the RESET and
ILOSS pins to implement the required maintenance
states.
The multiframing controller, when enabled, allows the S
and Q channels on the S/T-interface to be manipulated
by the microprocessor. When disabled, the S- and Q-
channel bits are automatically loaded with their default
values for applications not supporting multiframing.
The control flow state machine performs the functions
of reserved bit insertion, automatic implementation of
the ANSI maintenance state machine, and automatic
prioritization of multiple requests, such as reset, activa-
tion, maintenance, etc. Some bits that are normally
controlled by the control flow state machine can be
forced to their active state by writing the appropriate
register (i.e., register GR1). When the control flow state
machine is disabled (via the AUTOCTL bit in register
GR0), the only change in the operation is that reserved
bit control and ANSI maintenance control are passed
directly to the microprocessor via register CFR0.
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