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參數(shù)資料
| 型號： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 104/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
100
Lucent Technologies Inc.
Questions and Answers
(continued)
Miscellaneous
(continued)
A43:
(continued)
The crystal characteristics section of the data
sheet notes that the board parasitics must be
within the range of 0.6 pF
±
0.4 pF.
Q44:
What clocks are available on the T7256
A44:
The following clocks are available and are always
present once enabled, regardless of the state of
activation on the U- or S/T-interfaces:
1. SYN8K, pin 4 (8 kHz clock) is enabled by hold-
ing SDI (pin 12) low during an external RESET.
2. TDMCLK, pin 9 (2.048 MHz clock) is enabled
by writing TDMEN = 0 (register GR2, bit 5).
3. CKOUT, pin 17 (10.24 MHz or 15.36 MHz
clock) is enabled by writing register GRO bit 2
or 1, respectively, to 0. Normally 3-stated.
Note that using clocks 2 or 3 above requires a
microprocessor for setting the appropriate config-
uration.
Q45:
I plan to program the T7256 to output
15.36 MHz from its CKOUT pin. Is this clock a
buffered version of the 15.36 MHz oscillator
clock I am concerned that if it is not buffered, the
capacitive loading on this pin could affect the sys-
tem clock frequency.
A45:
The 15.36 MHz output is a buffered version of the
XTAL clock and therefore hanging capacitance
on it will not affect the T7256’s system clock fre-
quency.
Q46:
How does the filtering at the OPTOIN input work
A46:
The signals applied to OPTOIN are digitally fil-
tered for 20 ms. Any transitions under 20 ms will
be ignored.
Q47:
What is the isolation voltage of the 6N139
optoisolator used in the dc termination circuit of
the T7256
A47:
2500 VAC, 1 minute.
Q48:
Can the T7256 operate with an external
15.36 MHz clock source instead of using a crys-
tal
A48:
Yes, by leaving X1 disconnected and driving X2
with an external CMOS-level oscillator.
Q49:
What is the effect of ramping down the power-
supply voltage on the device When will it provide
a valid reset This condition can occur when a
line-powered NT1’s line cord is repeatedly
plugged in and removed and plugged in again
before the power supply has had enough time to
fully ramp-up.
A49:
The device’s reset is more dependent on the
RESET pin than the power supply to the device.
As long as the proper input conditions on the
RESET pin (see Table 42) are met, the device will
have a valid reset. Note that this input is a
Schmitt-trigger input.
Q50:
Is there a recommended method for powering the
T7256 For example, is it desirable to separate
the power supplies, etc.
A50:
The T7256 is not extremely sensitive to power-
supply schemes. Following standard practices of
decoupling power supplies close to the chip and,
if power and ground planes are not used, keeping
power traces away from high-frequency signals,
etc., should yield acceptable results. Separating
the T7256 analog power supplies from the digital
power supplies near the chip may yield a small
improvement, and the same holds true for using
power and ground planes vs. discrete traces.
Note that if analog and digital power supplies are
separated, the crystal power supply (V
DDO
)
should be tied to the digital supplies (V
DDD
).
See the SCNTI Family Reference Design Board
Hardware User Manual (MN96-011ISDN),
Appendix A for an example of a board layout that
performs well.
Q51:
What are the filter characteristics of the PLL at
the NT
A51:
The –3 dB frequency is approximately 5 Hz,
peaking is about 1.2 dB.
Q52:
Can the T7256 operate in the LT mode
A52:
No, the T7256 is optimized for the NT side of the
loop and cannot operate in the LT mode.
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