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參數(shù)資料
| 型號(hào)： | T7234A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 40/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
36
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 21. S/T-Interface Interrupt Register (Address 15h)
These bits are cleared during RESET.
Table 22. S/T-Interface Interrupt Mask Register (Address 16h)
Reg
SIR0
R/W
R
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
I4C
Bit 2
SFECV
Bit 1
QSC
Bit 0
SOM
Register
SIR0
Bit
0
Symbol
SOM
Name/Description
Start of Multiframe.
Activates (set to 1) upon transmission of the F bit that begins
a multiframing interval toward the TE. Bit is cleared on read.
0 to 1—Start of multiframe.
Q-Bits State Change.
Activates (set to 1) when the set of four Q bits received in
a multiframe differs from the set of Q bits received in the previous multiframe. Bit
is cleared on read.
0—No state change.
1—State change.
S-Channel Far-End Code Violation.
Activates when an illegal line code violation
or extra/missing bipolar violations are detected in the S/T-interface data stream.
Changes on multiframe boundary. Only active if MULTIF = 0 (register GR0, bit 5)
and a transparent Loop2 is not in effect. Bit is cleared on read.
0—No code violations.
1—At least one code violation.
INFO 4 Change.
0—No INFO 4 state change.
1—INFO 4 state change.
SIR0
1
QSC
SIR0
2
SFECV
SIR0
3
I4C
Reg
SIR1
R/W
R/W
Bit 7
—
—
Bit 6
—
—
Bit 5
—
—
Bit 4
—
—
Bit 3
I4CM
1
Bit 2
SFECVM
1
Bit 1
QSCM
1
Bit 0
SOMM
1
Default State on RESET
Register
SIR1
Bit
0
Symbol
SOMM
Name/Description
Start of Multiframe Mask.
0—SOM interrupt enabled.
1—SOM interrupt disabled (default).
Q-Bits State Change Mask.
0—QSC interrupt enabled.
1—QSC interrupt disabled (default).
S-Subchannel Far-End Code Violation Mask.
0—SFECVM interrupt enabled.
1—SFECVM interrupt disabled (default).
INFO 4 Change Mask.
0—I4C interrupt enabled.
1—I4C interrupt disabled (default).
SIR1
1
QSCM
SIR1
2
SFECVM
SIR1
3
I4CM
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