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參數(shù)資料
| 型號(hào)： | SYM53C875 |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁(yè)數(shù)： | 92/243頁(yè) |
| 文件大小： | 1362K |
| 代理商： | SYM53C875 |
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SCSI Operating Registers
5-6
SYM53C875/875E Data Manual
bit 4 in the SCNT L1 register should be
checked to verify that the SYM53C875 did not
connect to the SCSI bus.
Bit 4
WAT N (Select with SAT N/ on a Start
Sequence)
When this bit is set and the SYM53C875 is in
initiator mode, the SAT N/ signal will be
asserted during SYM53C875 selection of a
SCSI target device. T his is to inform the target
that the SYM53C875 has a message to send. If
a selection time-out occurs while attempting to
select a target device, SAT N/ will be deasserted
at the same time SSEL/ is deasserted. When
this bit is clear, the SAT N/ signal will not be
asserted during selection. When executing
SCSI SCRIPT S, this bit is controlled by the
SCRIPT S processor, but it may be set manu-
ally in low level mode.
Bit 3
E PC (E nable Parity Checking)
When this bit is set, the SCSI data bus is
checked for odd parity when data is received
from the SCSI bus in either initiator or target
mode. Parity is also checked as data goes from
the SCSI FIFO to the DMA FIFO. If a parity
error is detected, bit 0 of the SIST 0 register is
set and an interrupt may be generated.
If the SYM53C875 is operating in initiator
mode and a parity error is detected, SAT N/
can optionally be asserted, but the transfer
continues until the target changes phase. When
this bit is cleared, parity errors are not
reported.
When these bits are set in the SYM53C875N,
the chip again checks inbound SCSI parity at
the SCSI FIFO—DMA FIFO interface after
the data has passed through the SCSI FIFO.
T he parity bits are not passed through the
DMA FIFO, but parity is generated before the
data is sent out on the PCI bus.
Bit 2
Reserved
Bit 1
AAP (Assert SAT N/ on Parity E rror)
When this bit is set, the SYM53C875 automat-
ically asserts the SAT N/ signal upon detection
of a parity error. SAT N/ is only asserted in ini-
tiator mode. T he SAT N/ signal is asserted
before deasserting SACK / during the byte
transfer with the parity error. T he Enable Par-
ity Checking bit must also be set for the
SYM53C875 to assert SAT N/ in this manner.
A parity error is detected on data received from
the SCSI bus.
If the Assert SAT N/ on Parity Error bit is
cleared or the Enable Parity Checking bit is
cleared, SAT N/ will not be automatically
asserted on the SCSI bus when a parity error is
received.
Bit 0
T RG (Target Mode)
T his bit determines the default operating mode
of the SYM53C875. T he user must manually
set target or initiator mode. T his can be done
using the SCRIPT S language (SET TARGET
or CLEAR TARGET ). When this bit is set, the
chip is a target device by default. When this bit
is cleared, the SYM53C875 is an initiator
device by default.
CAUT ION:
Writing this bit while not connected may cause the
loss of a selection or reselection due to the chang-
ing of target or initiator modes.
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