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參數(shù)資料
| 型號(hào)： | SYM53C875 |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁(yè)數(shù)： | 110/243頁(yè) |
| 文件大?。?/td> | 1362K |
| 代理商： | SYM53C875 |
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SCSI Operating Registers
5-24
SYM53C875/875E Data Manual
Bit 3
CON (Connected)
T his bit is automatically set any time the
SYM53C875 is connected to the SCSI bus as
an initiator or as a target. It will be set after
successfully completing selection or when the
SYM53C875 has responded to a bus-initiated
selection or reselection. It will also be set after
the SYM53C875 wins arbitration when oper-
ating in low level mode. When this bit is clear,
the SYM53C875 is not connected to the SCSI
bus.
Bit 2
INT F (Interrupt on the Fly)
T his bit is asserted by an INT FLY instruction
during SCRIPT S execution. SCRIPT S pro-
grams will not halt when the interrupt occurs.
T his bit can be used to notify a service routine,
running on the main processor while the
SCRIPT S processor is still executing a
SCRIPT S program. If this bit is set, when the
ISTAT register is read it will not automatically
be cleared. To clear this bit, it must be written
to a one. T he reset operation is self-clearing.
Note: If the INT F bit is set but SIP or DIP is not
set, do not attempt to read the other chip
status registers. An interrupt-on-the-fly
interrupt must be cleared before servicing
any other interrupts indicated by SIP or
DIP.
Note: T his bit must be written to one in order to
clear it after it has been set.
Bit 1
SIP (SCSI Interrupt Pending)
T his status bit is set when an interrupt condi-
tion is detected in the SCSI portion of the
SYM53C875.
T he following conditions will cause a SCSI
interrupt to occur:
I
A phase mismatch (initiator mode) or
SAT N/ becomes active (target mode)
I
An arbitration sequence completes
I
A selection or reselection time-out occurs
I
T he SYM53C875 was selected
I
T he SYM53C875 was reselected
I
A SCSI gross error occurs
I
An unexpected disconnect occurs
I
A SCSI reset occurs
I
A parity error is detected
I
T he handshake-to-handshake timer is
expired
I
T he general purpose timer is expired.
To determine exactly which condition(s)
caused the interrupt, read the SIST 0 and
SIST 1 registers.
Bit 0
DIP (DMA Interrupt Pending)
T his status bit is set when an interrupt condi-
tion is detected in the DMA portion of the
SYM53C875. T he following conditions will
cause a DMA interrupt to occur:
I
A PCI parity error is detected
I
A bus fault is detected
I
An abort condition is detected
I
A SCRIPT S instruction is executed in
single-step mode
I
A SCRIPT S interrupt instruction is
executed
I
An illegal instruction is detected.
To determine exactly which condition(s)
caused the interrupt, read the DSTAT register.
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