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參數(shù)資料
| 型號(hào)： | SYM53C875 |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁(yè)數(shù)： | 40/243頁(yè) |
| 文件大?。?/td> | 1362K |
| 代理商： | SYM53C875 |
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2-18
SYM53C875/875E Data Manual
Functional Description
Synchronous Operation
(Re)Select During
(Re)Selection
In multi-threaded SCSI I/O environments, it is not
uncommon to be selected or reselected while try-
ing to perform selection/reselection. T his situation
may occur when a SCSI controller (operating in
initiator mode) tries to select a target and is rese-
lected by another. T he Select SCRIPT S instruc-
tion has an alternate address to which the
SCRIPT S will jump when this situation occurs.
T he analogous situation for target devices is being
selected while trying to perform a reselection.
Once a change in operating mode occurs, the initi-
ator SCRIPT S should start with a Set Initiator
instruction or the target SCRIPT S should start
with a Set Target instruction. T he Selection and
Reselection Enable bits (SCID bits 5 and 6,
respectively) should both be asserted so that the
SYM53C875 may respond as an initiator or as a
target. If only selection is enabled, the
SYM53C875 cannot be reselected as an initiator.
T here are also status and interrupt bits in the
SIST 0 and SIEN0 registers, respectively, indicat-
ing that the SYM53C875 has been selected (bit 5)
and reselected (bit 4).
Synchronous Operation
T he SYM53C875 can transfer synchronous SCSI
data in both initiator and target modes. T he
SX FER register controls both the synchronous off-
set and the transfer period. It may be loaded by the
CPU before SCRIPT S execution begins, from
within SCRIPT S via a Table Indirect I/O instruc-
tion, or with a Read-Modify-Write instruction.
T he SYM53C875 can receive data from the SCSI
bus at a synchronous transfer period as short as
50 ns, regardless of the transfer period used to
send data. T he SYM53C875 can receive data at
one-fourth of the divided SCLK frequency.
Depending on the SCLK frequency, the negoti-
ated transfer period, and the synchronous clock
divider, the SYM53C875 can send synchronous
data at intervals as short as 50 ns for Ultra SCSI,
100 ns for fast SCSI and 200 ns for SCSI-1.
Determining the
Data Transfer Rate
Synchronous data transfer rates are controlled by
bits in two different registers of the SYM53C875.
A brief description of the bits is provided below.
Figure 2-5 illustrates the clock division factors
used in each register, and the role of the register
bits in determining the transfer rate.
SCNT L3 Register, bits 6–4 (SCF2–0)
T he SCF2-0 bits select the factor by which the fre-
quency of SCLK is divided before being presented
to the synchronous SCSI control logic. T he output
from this divider controls the rate at which data
can be received; this rate must not exceed 80
MHz. T he receive rate of synchronous SCSI data
is 1/4 of the SCF divider output. For example, if
SCLK is 80MHz and the SCF value is set to
divide by two, then the maximum rate at which
data can be received is 10 MHz (80/(2*4) = 10).
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