參數(shù)資料
型號(hào)： SYM53C875
廠商： LSI Corporation
英文描述： PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器)
中文描述： 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器）
文件頁(yè)數(shù)： 28/243頁(yè)
文件大?。?/td> 1362K
代理商： SYM53C875
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)
2-6
SYM53C875/875E Data Manual
Functional Description
JTAG Boundary Scan Testing
Control register at configuration addresses 34-35h
controls the GPIO0 and GPIO1 pins. For more
information on GPIO1-0 access, refer to the Serial
Interface Control register description in Chapter
3. For more information on the GPIO pins, see
Chapter 4. T his does not apply to the
SYM53C875E.
Note: T he Symbios SDMS software controls the
GPIO0 and GPIO1 pins via the GPCNT L
and GPREG registers. T herefore, if using
SDMS, do not connect a 4.7 K
resistor
between MAD(7) and Vss.
JTAG Boundary Scan
Testing
T he SYM53C875J/53C875N/53C875JB include
support for JTAG boundary scan testing in accor-
dance with the IEEE 1149.1 specification, with
one exception that is discussed in this section. T he
device can accept all required boundary scan
instructions, as well as the optional CLAMP,
HIGHZ, and IDCODE instructions.
T he SYM53C875J/53C875N/53C875JB use an
8-bit instruction register to support all boundary
scan instructions. T he data registers included in
the device are the Boundary Data register, the
IDCODE register, and the Bypass register. T he
device can handle a 10 MHz T CK frequency for
T DO and T DI.
Due to design constraints, the RST / pin (System
Reset) will always tri-state the SCSI pins when it is
asserted. T his action cannot be controlled by the
boundary scan logic, and thus is not compliant
with the specification. T here are two solutions that
resolve this issue:
1. Use the RST / pin as a boundary scan
compliance pin. When the pin is deasserted,
the device is boundary scan compliant and
when asserted, the device is non-compliant. To
maintain compliance, the RST / pin must be
driven high.
2. When RST / is asserted during boundary scan
testing, the expected output on the SCSI pins
must be a high-z condition, and not what is
contained in the boundary scan data registers
for the SCSI pin output cells.
Because of package limitations, the SYM53C875J/
53C875JB replaces the T EST IN, MAC/
_T EST OUT, BIG_LIT /, and SDIRP1 signals with
the JTAG boundary scan signals. T he
SYM53C875N includes support for these signals
in addition to the JTAG pins.
Big and Little Endian
Support
T he SYM53C875/53C875N supports both Big
and Little Endian byte ordering through pin selec-
tion. T he SYM53C875J/53C875JB operates in
Little Endian mode only (the BIG_LIT pin is
replaced by one of the JTAG boundary scan sig-
nals). In Big Endian mode, the first byte of an
aligned SCSI-to-PCI transfer will be routed to lane
three and succeeding transfers will be routed to
descending lanes. T his mode of operation also
applies to data transfers over the add-in ROM
interface. T he byte of data accessed at location
0000h from memory is routed to lane three, and
the data at location 0003h is routed to byte lane 0.
In Little Endian mode, the first byte of an aligned
SCSI to PCI transfer will be routed to lane zero
and succeeding transfers will be routed to ascend-
ing lanes. T his mode of operation also applies to
the add-in ROM interface. T he byte of data
accessed at location 0000h from memory is routed
to lane zero, and the data at location 0003h is
routed to byte lane 3.
T he Big_Lit pin gives the SYM53C875 the flexi-
bility of operating with either Big or Little Endian
byte orientation. Internally, in either mode, the
actual byte lanes of the DMA FIFO and registers
are not modified. T he SYM53C875 supports slave
accesses in Big or Little Endian mode.
相關(guān)PDF資料
PDF描述
SYM53C875E PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器)
SYM53C876E PCI-Dual Channel SCSI Multi-function Controller(PCI-雙通道SCSI多功能控制器)
SYM53C876 PCI-Dual Channel SCSI Multi-Function Controller(PCI 雙通道SCSI多功能控制器)
SYM53C895A PCI to Ultra2 SCSI Controller(PCI與Ultra2 SCSI連接控制器)
SYM53C895 PCI to Ultra2 SCSI I/O Processor with LVD（Low Voltage Differential Link）Universal Transceivers(PCI與Ultra2 SCSI I/O接口處理器（帶低電壓差分連接通用收發(fā)器）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SYM53C876E(PBGA) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller
SYM53C876E(PQFP) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller
SYM53C885 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
SYM53C896 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER
SYM-63LH+ 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:Frequency Mixer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*