參數(shù)資料
型號(hào)： SYM53C875
廠商： LSI Corporation
英文描述： PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器)
中文描述： 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器）
文件頁(yè)數(shù)： 109/243頁(yè)
文件大小： 1362K
代理商： SYM53C875
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SCSI Operating Registers
SYM53C875/875E Data Manual
5-23
Register 14 (94)
Interrupt Status (ISTAT )
(Read/Write)
T his is the only register that can be accessed by the
host CPU while the SYM53C875 is executing
SCRIPT S (without interfering in the operation of
the SYM53C875). It may be used to poll for inter-
rupts if hardware interrupts are disabled. T here
may be stacked interrupts pending; read this regis-
ter after servicing an interrupt to check for stacked
interrupts. For more information on interrupt han-
dling refer to Chapter 2, “Functional Description.”
Bit 7
ABRT (Abort Operation)
Setting this bit aborts the current operation
being executed by the SYM53C875. If this bit
is set and an interrupt is received, reset this bit
before reading the DSTAT register to prevent
further aborted interrupts from being gener-
ated. T he sequence to abort any operation is:
1. Set this bit.
2. Wait for an interrupt.
3. Read the ISTAT register.
4. If the SCSI Interrupt Pending bit is set,
then read the SIST 0 or SIST 1 register to
determine the cause of the SCSI Interrupt
and go back to Step 2.
5. If the SCSI Interrupt Pending bit is clear,
and the DMA Interrupt Pending bit is set,
then write 00h value to this register.
6. Read the DSTAT register to verify the
aborted interrupt and to see if any other
interrupting conditions have occurred.
Bit 6
SRST (Software Reset)
Setting this bit resets the SYM53C875. All
operating registers are cleared to their respec-
tive default values and all SCSI signals are
deasserted. Setting this bit does not cause the
SCSI RST / signal to be asserted. T his reset will
not clear the 53C700 Compatibility bit or any
of the PCI configuration registers. T his bit is
not self-clearing; it must be cleared to clear the
reset condition (a hardware reset will also clear
this bit).
Bit 5
SIGP (Signal Process)
SIGP is a R/W bit that can be written at any
time, and polled and reset via CT EST 2. T he
SIGP bit can be used in various ways to pass a
flag to or from a running SCRIPT S instruc-
tion.
T he only SCRIPT S instruction directly
affected by the SIGP bit is Wait For Selection/
Reselection. Setting this bit causes that
instruction to jump to the alternate address
immediately. T he instructions at the alternate
jump address should check the status of SIGP
to determine the cause of the jump. T he SIGP
bit may be used at any time and is not
restricted to the wait for selection/ reselection
condition.
Bit 4
SE M (Semaphore)
T his bit can be set by the SCRIPT S processor
using a SCRIPT S register write instruction.
T he bit may also be set by an external proces-
sor while the SYM53C875 is executing a
SCRIPT S operation. T his bit enables the
SYM53C875 to notify an external processor of
a predefined condition while SCRIPT S are
running. T he external processor may also
notify the SYM53C875 of a predefined condi-
tion and the SCRIPT S processor may take
action while SCRIPT S are executing.
ABRT
7
SRST
6
SIGP
5
SEM
4
CON
3
INTF
2
SIP
1
DIP
0
Default>>>
0
0
0
0
0
0
0
0
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