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參數(shù)資料
| 型號： | SYM53C875 |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個PCI -超的SCSI的I / O處理器） |
| 文件頁數(shù)： | 46/243頁 |
| 文件大?。?/td> | 1362K |
| 代理商： | SYM53C875 |
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2-24
SYM53C875/875E Data Manual
Functional Description
Chained Block Moves
Sample Interrupt
Service Routine
T he following is a sample of an interrupt service
routine for the SYM53C875. It can be repeated if
polling is used, or should be called when the IRQ/
pin is asserted if hardware interrupts are used.
1. Read ISTAT.
2. If the INT F bit is set, it must be written to a
one to clear this status.
3. If only the SIP bit is set, read SIST 0 and
SIST 1 to clear the SCSI interrupt condition
and get the SCSI interrupt status. T he bits in
the SIST 0 and SIST 1 tell which SCSI
interrupt(s) occurred and determine what
action is required to service the interrupt(s).
4. If only the DIP bit is set, read the DSTAT to
clear the interrupt condition and get the DMA
interrupt status. T he bits in the DSTAT will
tell which DMA interrupt(s) occurred and
determine what action is required to service
the interrupt(s).
5. If both the SIP and DIP bits are set, read
SIST 0, SIST 1, and DSTAT to clear the SCSI
and DMA interrupt condition and get the
interrupt status. If using 8-bit reads of the
SIST 0, SIST 1, and DSTAT registers to clear
interrupts, insert a 12 CLK delay between the
consecutive reads to ensure that the interrupts
clear properly. Both the SCSI and DMA
interrupt conditions should be handled before
leaving the ISR. It is recommended that the
DMA interrupt be serviced before the SCSI
interrupt, because a serious DMA interrupt
condition could influence how the SCSI
interrupt is acted upon.
6. When using polled interrupts, go back to step
1 before leaving the interrupt service routine,
in case any stacked interrupts moved in when
the first interrupt was cleared. When using
hardware interrupts, the IRQ/ pin will be
asserted again if there are any stacked
interrupts. T his should cause the system to re-
enter the interrupt service routine.
Chained Block Moves
Since the SYM53C875 has the capability to trans-
fer 16-bit wide SCSI data, a unique situation
occurs when dealing with odd bytes. T he chained
move (CHMOV) SCRIPT S instruction along with
the Wide SCSI Send (WSS) and Wide SCSI
Receive (WSR) bits in the SCNT L2 register are
used to facilitate these situations. T he Chained
Block Move instruction is illustrated in Figure 2-6.
Wide SCSI Send
Bit
T he WSS bit is set whenever the SCSI core is
sending data (Data Out for initiator or Data In for
target) and the core detects a partial transfer at the
end of a chained Block Move SCRIPT S instruc-
tion (this flag will not be set if a normal Block
Move instruction is used). Under this condition,
the SCSI core does not send the low-order byte of
the last partial memory transfer across the SCSI
bus. Instead, the low-order byte is temporarily
stored in the lower byte of the SODL register and
the WSS flag is set. T he hardware uses the WSS
flag to determine what behavior must occur at the
start of the next data send transfer. When the WSS
flag is set at the start of the next transfer, the first
byte (the high-order byte) of the next data send
transfer is “married” with the stored low-order
byte in the SODL register; and the two bytes are
sent out across the bus, regardless of the type of
Block Move instruction (normal or chained). T he
flag is automatically cleared when the “married”
word is sent. T he flag can alternately be cleared
through SCRIPT S or by the microprocessor.
Additionally, this bit can be used by the micropro-
cessor or SCRIPT S for error detection and recov-
ery purposes.
Wide SCSI Receive
Bit
T he WSR bit is set whenever the SCSI core is
receiving data (Data In for initiator or Data Out
for target) and the core detects a partial transfer at
the end of a block move or chained block move
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