參數(shù)資料
型號(hào): SYM53C875
廠商: LSI Corporation
英文描述: PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器)
中文描述: 的PCI -超的SCSI I / O處理器(個(gè)PCI -超的SCSI的I / O處理器)
文件頁(yè)數(shù): 127/243頁(yè)
文件大?。?/td> 1362K
代理商: SYM53C875
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SCSI Operating Registers
SYM53C875/875E Data Manual
5-41
Register 41 (C1)
SCSI Interrupt Enable One (SIEN1)
Read/Write
T his register contains the interrupt mask bits corre-
sponding to the interrupting conditions described
in the SIST 1 register. An interrupt is masked by
clearing the appropriate mask bit. For more infor-
mation on interrupts, refer to Chapter 2, “Func-
tional Description.”
Bits 7-3 Reserved
Bit 2
ST O (Selection or Reselection T ime-
out)
T he SCSI device which the SYM53C875 was
attempting to select or reselect did not respond
within the programmed time-out period. See
the description of the ST IME0 register bits 3-0
for more information on the time-out timer.
Bit 1
GE N (General Purpose T imer
E xpired)
T he general purpose timer has expired. T he
time measured is the time between enabling
and disabling of the timer. See the description
of the ST IME1 register, bits 3-0, for more
information on the general purpose timer.
Bit 0
HT H ( Handshake-to-Handshake
T imer E xpired)
T he handshake-to-handshake timer has
expired. T he time measured is the SCSI
Request-to-Request (target) or Acknowledge-
to-Acknowledge (initiator) period. See the
description of the ST IME0 register, bits 7-4,
for more information on the handshake-to-
handshake timer.
RES
7
RES
6
RES
5
RES
4
RES
3
STO
2
GEN
1
HTH
0
Default>>>
X
X
X
X
X
0
0
0
Register 42 (C2)
SCSI Interrupt Status Zero (SIST 0)
Read Only
Reading the SIST 0 register returns the status of the
various interrupt conditions, whether they are en-
abled in the SIEN0 register or not. Each bit set in-
dicates that the corresponding condition has
occurred. Reading the SIST 0 will clear the inter-
rupt status.
Reading this register will clear any bits that are set
at the time the register is read, but will not neces-
sarily clear the register because additional inter-
rupts may be pending (the SYM53C875 stacks
interrupts). SCSI interrupt conditions may be indi-
vidually masked through the SIEN0 register.
When performing consecutive 8-bit reads of the
DST AT , SIST 0, and SIST 1 registers (in any or-
der), insert a delay equivalent to 12 CLK periods
between the reads to ensure the interrupts clear
properly. Also, if reading the registers when both
the IST AT SIP and DIP bits may not be set, the
SIST 0 and SIST 1 registers should be read before
the DST AT register to avoid missing a SCSI inter-
rupt. For more information on interrupts, refer to
Chapter 2, “Functional Description.”
Bit 7
M/A (Initiator Mode: Phase Mis-
match; Target Mode: SAT N/ Active)
In initiator mode, this bit is set if the SCSI
phase asserted by the target does not match the
instruction. T he phase is sampled when SREQ/
is asserted by the target. In target mode, this
bit is set when the SAT N/ signal is asserted by
the initiator.
Bit 6
CMP (Function Complete)
T his bit is set when an arbitration only or full
arbitration sequence has completed.
M/A
7
CMP
6
SEL
5
RSL
4
SGE
3
UDC
2
RST
1
PAR
0
Default>>>
0
0
0
0
0
0
0
0
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