參數(shù)資料
型號(hào)： SYM53C875
廠商： LSI Corporation
英文描述： PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器)
中文描述： 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器）
文件頁(yè)數(shù)： 27/243頁(yè)
文件大?。?/td> 1362K
代理商： SYM53C875
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Functional Description
PCI Cache Mode
SYM53C875/875E Data Manual
2-5
To use one of the configurations mentioned above
in a host adapter board design, put 4.7 K
pull-
down resistors on the MAD pins corresponding to
the available memory space. For example, to con-
nect to a 32 K B external ROM, use pull-downs on
MAD(3) and MAD(2). If the external memory
interface is not used, then no external resistors are
necessary since there are internal pull-ups on the
MAD bus. T he internal pull-up resistors are dis-
abled when external pull-down resistors are
detected, to reduce current drain.
T he SYM53C875 allows the system to determine
the size of the available external memory using the
Expansion ROM Base Address register in PCI
configuration space. For more information on how
this works, refer to the PCI specification or the
Expansion ROM Base Address register description
in Chapter 3.
MAD(0) is the slow ROM pin. When pulled down,
it enables two extra clock cycles of data access time
to allow use of slower memory devices. T he exter-
nal memory interface also supports updates to
flash memory. T he 12 volt power supply for flash
memory, V
PP
, is enabled and disabled with the
GPIO4 pin and the GPIO4 control bit. For more
information on the GPIO4 pin, refer to Chapter 4.
PCI Cache Mode
T he SYM53C875 supports the PCI specification
for an 8-bit Cache Line Size register located in
PCI configuration space. T he Cache Line Size reg-
ister provides the ability to sense and react to non-
aligned addresses corresponding to cache line
boundaries. In conjunction with the Cache Line
Size register, the PCI commands Read Line, Read
Multiple, and Write and Invalidate are each soft-
ware enabled or disabled to allow the user full flex-
ibility in using these commands. For more
information on PCI cache mode operations, refer
to Chapter 3.
Load/Store Instructions
T he SYM53C875 supports the Load/Store
instruction type, which simplifies the movement of
data between memory and the internal chip regis-
ters. It also enables the SYM53C875 to transfer
bytes to addresses relative to the DSA register. For
more information on the Load and Store instruc-
tions, refer to Chapter 6.
3.3 Volt/5 Volt PCI Interface
T he SYM53C875 can attach directly to a 3.3 Volt
or a 5 Volt PCI interface, due to separate V
DD
pins
for the PCI bus drivers. T his allows the devices to
be used on the universal board recommended by
the PCI Special Interest Group.
Additional Access to
General Purpose Pins
T he SYM53C875 can access the GPIO0 and
GPIO1 general purpose pins through register bits
in the PCI configuration space, instead of using
the GPCNT L register in the operating register
space to control these pins. In the Symbios SDMS
software, the configuration bits control pins as the
clock and data lines, respectively.
To access the GPIO1-0 pins through the configu-
ration space, connect a 4.7 K
resistor between
the MAD(7) pin and V
SS
. MAD(7) contains an
internal pull-up that is sensed shortly after chip
reset. If the pin is sensed high, GPIO1-0 access is
disabled; if it is low, GPIO1-0 access is enabled.
Additionally, if GPIO1-0 access has been enabled
through the MAD(7) pin and if GPIO0 and/or
GPIO1 are sensed low after chip reset, GPIO1-0
access will be disabled. If GPIO1-0 access through
configuration space is enabled, the GPIO0 and
GPIO1 pins cannot be controlled from the
GPCNT L and GPREG registers, but will be
observable from the GPREG register. When
GPIO1-0 access is enabled, the Serial Interface
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