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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 9/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SNA7412ZHK |
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PC Card Controller Programming Model
90
September 2005
SCPS110
Table 48. System Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
2016
RSVD
RW
These bits are reserved. Do not change the value of these bits.
15 §
MRBURSTDN
RW
Memory read burst enable downstream. When this bit is set, the controller allows memory read
transactions to burst downstream.
0 = MRBURSTDN downstream is disabled
1 = MRBURSTDN downstream is enabled (default)
14 §
MRBURSTUP
RW
Memory read burst enable upstream. When this bit is set, the controller allows memory read
transactions to burst upstream.
0 = MRBURSTUP upstream is disabled (default)
1 = MRBURSTUP upstream is enabled
13
SOCACTIVE
R
Socket activity status. When set, this bit indicates access has been performed to or from a PC Card.
Reading this bit causes it to be cleared.
0 = No socket activity (default)
1 = Socket activity
12
RSVD
R
Reserved. This bit returns 1b when read.
11
PWRSTREAM
R
Power-stream-in-progress status bit. When set, this bit indicates that a power stream to the power
switch is in progress and a powering change has been requested. When this bit is cleared, it indicates
that the power stream is complete.
0 = Power stream is complete, delay has expired (default)
1 = Power stream is in progress
10
DELAYUP
R
Power-up delay-in-progress status bit. When set, this bit indicates that a power-up stream has been
sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up
delay has expired.
0 = Power-up delay has expired (default)
1 = Power-up stream sent to switch. Power might not be stable.
9
DELAYDOWN
R
Power-down delay-in-progress status bit. When set, this bit indicates that a power-down stream has
been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
0 = Power-down delay has expired (default)
1 = Power-down stream sent to switch. Power might not be stable.
8
INTERROGATE
R
Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when
the interrogation completes.
0 = Interrogation not in progress (default)
1 = Interrogation in progress
7
RSVD
R
Reserved. This bit returns 0b when read.
6 §
PWRSAVINGS
RW
Power savings mode enable. When this bit is set, the controller consumes less power with no
performance loss.
0 = Power savings mode disabled
1 = Power savings mode enabled (default)
5 §
SUBSYSRW
RW
Subsystem ID and subsystem vendor ID, ExCA ID and revision register read/write enable. This bit also
controls read/write for the function 2 subsystem ID register.
0 = Registers are read/write
1 = Registers are read-only (default)
4 §
CB_DPAR
RW
CardBus data parity SERR signaling enable.
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
3 §
RSVD
R
Reserved. This bit returns 0b when read.
2
EXCAPOWER
R
ExCA power control bit.
0 = Enables 3.3 V (default)
1 = Enables 5 V
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
These bits are cleared only by the assertion of GRST.
§ These bits are global in nature and must be accessed only through function 0.
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